[00/11] TI C6X binutils port: introduction

["Joseph S. Myers" <joseph at codesourcery dot com>]

This patch series adds a binutils port to the TMS320C6000 (TI C6X)
processor family.  This is an exposed pipeline VLIW DSP, commonly
found on devices such as TI OMAP that also contain ARM cores.

CodeSourcery is working on a full toolchain port to this processor,
including GCC, GDB, Newlib and uClibc (for use with the uClinux port
to this processor).  This port uses TI's new ELF ABI and is unrelated
to various previous attempts at ports to this processor, generally
COFF-based and not assigned to the FSF.

There are eleven patches in this series.  The first four are changes
that are logically target-independent and I think can sensibly be
considered independently of each other and of the port, though their
motivation is for use in the port.  Patch 5 is the toplevel configure
changes.  Patches 6-11 are the port proper, divided up into
directories but intended all to be committed together.  The patch
series also depends on a config.sub patch to improve config.sub
handling of the relevant target triplets (approved for but not yet
committed to config.git; attached to this message for information).

I am willing to serve as maintainer for this port, as indicated by the
MAINTAINERS change in patch 9.

The code has been written using processor manuals SPRU731 (July 2006),
SPRU733A (November 2006), SPRU732H (October 2008) and SPRUFE8 (October
2008), and EABI SPRAB89 (version 0.6, 30 December 2009, parts not yet
written, not yet publicly available).  In the course of writing it,
many places have been found where the manuals are unclear or contain
mistakes; these have been clarified with TI and should be corrected in
future versions of the manuals.  I have tried to include comments in
the code in the most important places where it deviates from the
manuals because of such corrections and clarifications, but please ask
if in doubt about whether any particular deviation is deliberate.

This is an initial port that I think is sufficient to be useful.
Other features expected to be added in due course include:

* REL support in the linker.

* 16-bit instruction disassembly and assembly.

* Improvements to code alignment support in the assembler.

* Resource constraint checks for the many constraints on what
  instructions can be used together.

* Build attributes, like the ARM EABI, once the relevant ABI section
  is written.

* More testcases for various aspects of the assembler and
  disassembler.

* Dynamic linking support using the DSBT shared library model.

* Exception handling support (similar to ARM EABI, but using
  .cfi_sections with standard CFI directives to generate unwind
  information if possible).

OK to commit (any or all of the 11 patches)?

-- 
Joseph S. Myers
joseph@codesourcery.com