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[RFA] Fix disassembly of Thumb-1 LDMIA
- From: Matthew Gretton-Dann <matthew dot gretton-dann at arm dot com>
- To: binutils at sourceware dot org
- Date: Tue, 11 May 2010 10:27:05 +0100
- Subject: [RFA] Fix disassembly of Thumb-1 LDMIA
Hi,
The attached patch fixes opcodes/arm-dis.c's incorrect assumption that
all Thumb-1 LDMIA instructions have writeback. In fact the LDMIA
instruction has writeback if and only if the base register is not in the
list of registers to load into.
Please can someone review and approve this patch?
Thanks,
Matt
Proposed opcodes/ChangeLog:
2010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
format.
(print_insn_thumb16): Add support for new %W format.
--
Matthew Gretton-Dann
Principal Engineer - PD Software, Tools
ARM Ltd
Index: opcodes/arm-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/arm-dis.c,v
retrieving revision 1.124
diff -u -p -u -p -r1.124 arm-dis.c
--- opcodes/arm-dis.c 24 Feb 2010 15:11:42 -0000 1.124
+++ opcodes/arm-dis.c 11 May 2010 08:54:49 -0000
@@ -1161,6 +1161,7 @@ static const struct opcode32 arm_opcodes
%x print warning if conditional an not at end of IT block"
%X print "\t; unpredictable <IT:code>" if conditional
%I print IT instruction suffix and operands
+ %W print Thumb Writeback indicator for LDMIA
%<bitfield>r print bitfield as an ARM register
%<bitfield>d print bitfield as a decimal
%<bitfield>H print (bitfield * 2) as a decimal
@@ -1274,7 +1275,7 @@ static const struct opcode16 thumb_opcod
{ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
/* format 15 */
{ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
- {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"},
+ {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
/* format 17 */
{ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
/* format 16 */
@@ -3438,6 +3439,14 @@ print_insn_thumb16 (bfd_vma pc, struct d
}
break;
+ case 'W':
+ /* Print writeback indicator for a LDMIA. We are doing a
+ writeback if the base register is not in the register
+ mask. */
+ if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
+ func (stream, "!");
+ break;
+
case 'b':
/* Print ARM V6T2 CZB address: pc+4+6 bits. */
{