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[PATCH 5/8] add lwsync for E500


lwsync was defined after e500 core got in shape. Prior that point the
requirement for unknown bits in the L field was either to perform a full sync
(i.e. treat unknown bits in L field as L=0) or to throw an invalid opcode.
Unfortunately the e500 does the later.
This patch treats lwsync as sync if assembling in -me500 mode since this is
what the CPU should do anyway.
This patch intends to avoid throwing lot of replacing patches for software.

Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
---
 opcodes/ppc-opc.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index b92b504..c018200 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4469,11 +4469,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"lswi",	X(31,597),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, NB}},
 {"lsi",		X(31,597),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA0, NB}},
 
-{"lwsync",	XSYNC(31,598,1), 0xffffffff, PPC,	PPCNONE,	{0}},
+{"lwsync",	XSYNC(31,598,1), 0xffffffff, PPC,	E500,		{0}},
 {"ptesync",	XSYNC(31,598,2), 0xffffffff, PPC64,	PPCNONE,	{0}},
 {"sync",	X(31,598),	XSYNC_MASK,  PPCCOM,	BOOKE|PPC476,	{LS}},
 {"msync",	X(31,598),	0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
 {"sync",	X(31,598),	0xffffffff, BOOKE|PPC476, PPCNONE, {0}},
+{"lwsync",	X(31,598),	0xffffffff, E500,	PPCNONE,	{0}},
 {"dcs",		X(31,598),	0xffffffff,  PWRCOM,	PPCNONE,	{0}},
 
 {"lfdx",	X(31,599),	X_MASK,      COM,	PPCEFS,		{FRT, RA0, RB}},
-- 
1.7.1


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