[PATCH] opcodes/gas: blackfin: support OUTC debug insn

[Mike Frysinger <vapier at gentoo dot org>]

The disassembler has partial (but incomplete/broken) support already for
the pseudo debug insn OUTC, so let's fix it up and finish it.  And now
that the disassembler can handle it, make sure our assembler can output
it too.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

include/opcode/:
2010-09-21  Mike Frysinger  <vapier@gentoo.org>

	* bfin.h: Declare pseudoChr structs/defines.

opcode/:
2010-09-21  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
	(decode_pseudoOChar_0): New function.
	(_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.

gas/:
2010-09-21  Mike Frysinger  <vapier@gentoo.org>

	* config/bfin-aux.h (bfin_gen_pseudochr): New prototype.
	* config/tc-bfin.c (bfin_gen_pseudochr): New function.
	* config/bfin-parse.y: Call bfin_gen_pseudochr for OUTC tokens.
---
 gas/config/bfin-aux.h   |    1 +
 gas/config/bfin-parse.y |   16 ++++++++++++++++
 gas/config/tc-bfin.c    |   10 ++++++++++
 include/opcode/bfin.h   |   28 ++++++++++++++++++++++++++++
 opcodes/bfin-dis.c      |   21 +++++++++++++++++----
 5 files changed, 72 insertions(+), 4 deletions(-)

diff --git a/gas/config/bfin-aux.h b/gas/config/bfin-aux.h
index 638df31..465a6af 100755
--- a/gas/config/bfin-aux.h
+++ b/gas/config/bfin-aux.h
@@ -63,5 +63,6 @@ INSTR_T bfin_gen_calla (Expr_Node *, int);
 INSTR_T bfin_gen_linkage (int, int);
 INSTR_T bfin_gen_pseudodbg (int, int, int);
 INSTR_T bfin_gen_pseudodbg_assert (int, REG_T, int);
+INSTR_T bfin_gen_pseudochr (int);
 bfd_boolean bfin_resource_conflict (INSTR_T, INSTR_T, INSTR_T);
 INSTR_T bfin_gen_multi_instr (INSTR_T, INSTR_T, INSTR_T);
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index 747442c..f8bb744 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -212,6 +212,7 @@ extern int yylex (void);
 #define uimm5(x) EXPR_VALUE (x)
 #define imm6(x) EXPR_VALUE (x)
 #define imm7(x) EXPR_VALUE (x)
+#define uimm8(x) EXPR_VALUE (x)
 #define imm16(x) EXPR_VALUE (x)
 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
 #define uimm16(x) EXPR_VALUE (x)
@@ -3618,6 +3619,21 @@ asm_1:
 	  $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
 	}
 
+	| OUTC expr
+	{
+	  if (!IS_UIMM ($2, 8))
+	    return yyerror ("Constant out of range");
+	  notethat ("psedodbg_assert: OUTC uimm8\n");
+	  $$ = bfin_gen_pseudochr (uimm8 ($2));
+	}
+
+	| OUTC REG
+	{
+	  if (!IS_DREG ($2))
+	    return yyerror ("Dregs expected");
+	  notethat ("psedodbg_assert: OUTC dreg\n");
+	  $$ = bfin_gen_pseudodbg (2, $2.regno & CODE_MASK, 0);
+	}
 
 ;
 
diff --git a/gas/config/tc-bfin.c b/gas/config/tc-bfin.c
index 2c7e3ef..5eb7bb5 100644
--- a/gas/config/tc-bfin.c
+++ b/gas/config/tc-bfin.c
@@ -1820,6 +1820,16 @@ bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected)
   return GEN_OPCODE32 ();
 }
 
+INSTR_T
+bfin_gen_pseudochr (int ch)
+{
+  INIT (PseudoChr);
+
+  ASSIGN (ch);
+
+  return GEN_OPCODE16 ();
+}
+
 /* Multiple instruction generation.  */
 
 INSTR_T
diff --git a/include/opcode/bfin.h b/include/opcode/bfin.h
index ae7f8e9..40f3986 100755
--- a/include/opcode/bfin.h
+++ b/include/opcode/bfin.h
@@ -987,6 +987,34 @@ typedef struct
   PseudoDbg_Assert_code_bits,	 	PseudoDbg_Assert_code_mask	\
 };
 
+/*  pseudoChr
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_ch;
+  int mask_ch;
+  int bits_code;
+  int mask_code;
+} PseudoChr;
+
+#define PseudoChr_opcode	0xf900
+#define PseudoChr_ch_bits	0
+#define PseudoChr_ch_mask	0xff
+#define PseudoChr_code_bits	8
+#define PseudoChr_code_mask	0xff
+
+#define init_PseudoChr				\
+{						\
+  PseudoChr_opcode,				\
+  PseudoChr_ch_bits,	PseudoChr_ch_mask,	\
+  PseudoChr_code_bits,	PseudoChr_code_mask	\
+};
+
 /*  CaCTRL
 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c
index 00799d2..19b1925 100644
--- a/opcodes/bfin-dis.c
+++ b/opcodes/bfin-dis.c
@@ -4550,7 +4550,7 @@ decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
 
   else if (grp == 0 && fn == 2)
     {
-      OUTS (outf, "OUTC");
+      OUTS (outf, "OUTC ");
       OUTS (outf, dregs (reg));
     }
   else if (fn == 0)
@@ -4570,6 +4570,21 @@ decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
 }
 
 static int
+decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
+{
+  /* psedoOChar
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+     | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
+     +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
+  int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
+
+  OUTS (outf, "OUTC ");
+  OUTS (outf, uimm8 (ch));
+
+  return 2;
+}
+
+static int
 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
 {
   /* pseudodbg_assert
@@ -4713,10 +4728,8 @@ _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
     rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
   else if ((iw0 & 0xff00) == 0xf800)
     rv = decode_pseudoDEBUG_0 (iw0, outf);
-#if 0
   else if ((iw0 & 0xFF00) == 0xF900)
-    rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf);
-#endif
+    rv = decode_pseudoOChar_0 (iw0, outf);
   else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
     rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
 
-- 
1.7.2