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[MIPS] Change madd/maddu/msub/msubu/mult/multu to DSP rev1


Hi,

  All MIPS cores that implement MIPS DSP rev 1 actually do madd, maddu, msub, msubu, mult, multu
for four accumulators.  The MIPS DSP spec has moved these 6 instructions from DSP rev 2 to rev 1.
Here is the patch to reflect the change.

  I added 6 instructions to the DSP R1 test, and ran "make check" under GAS for the target of "mips-sde-elf".
No new failures.  Is it ok to commit?  Thanks!

Regards,
Chao-ying

Opcodes/ChangeLog
2010-10-20  Chao-ying Fu  <fu@mips.com>

        * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.

Gas/testsuite/ChangeLog
2010-10-20  Chao-ying Fu  <fu@mips.com>

        * gas/mips/mips32-dsp.d, gas/mips/mips32-dsp.s: Add madd, maddu, msub, msubu, mult, multu.

Index: mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.79
diff -u -p -r1.79 mips-opc.c
--- mips-opc.c	18 Oct 2010 00:15:35 -0000	1.79
+++ mips-opc.c	20 Oct 2010 23:51:06 -0000
@@ -834,13 +834,13 @@ const struct mips_opcode mips_builtin_op
 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1	},
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55	},
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1	},
-{"madd",    "7,s,t",	0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33	},
+{"madd",    "7,s,t",	0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32	},
 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
 {"maddp",   "s,t",      0x70000441, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	     0,		SMT	},
 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1	},
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55	},
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1	},
-{"maddu",   "7,s,t",	0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33	},
+{"maddu",   "7,s,t",	0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32	},
 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,	0,		N411    },
 {"max.ob",  "X,Y,Q",	0x78000007, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
@@ -943,10 +943,10 @@ const struct mips_opcode mips_builtin_op
 {"msub.ps",	"D,S,T",	0x71600019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1    	},
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55 },
-{"msub",    "7,s,t",	0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33	},
+{"msub",    "7,s,t",	0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32	},
 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1	},
 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55	},
-{"msubu",   "7,s,t",	0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33	},
+{"msubu",   "7,s,t",	0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32	},
 {"mtpc",    "t,P",	0x4080c801, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
 {"mtps",    "t,P",	0x4080c800, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
 {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	0,		I1|IOCT	},
@@ -1035,11 +1035,11 @@ const struct mips_opcode mips_builtin_op
 {"mulsl.ob", "S,k",	0x4bc00432, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
 {"mulsl.qh", "Y,Q",	0x78200432, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1	},
-{"mult",    "7,s,t",	0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33	},
+{"mult",    "7,s,t",	0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32	},
 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
 {"multp",   "s,t",	0x00000459, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	0,		SMT	},
 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1	},
-{"multu",   "7,s,t",	0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33	},
+{"multu",   "7,s,t",	0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32	},
 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
 {"mulu",    "d,s,t",	0x00000059, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
 {"neg",     "d,w",	0x00000022, 0xffe007ff,	WR_d|RD_t,		0,		I1	}, /* sub 0 */


Index: gas/mips/mips32-dsp.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips32-dsp.d,v
retrieving revision 1.4
diff -u -p -r1.4 mips32-dsp.d
--- gas/mips/mips32-dsp.d	6 Feb 2008 05:29:03 -0000	1.4
+++ gas/mips/mips32-dsp.d	21 Oct 2010 00:04:29 -0000
@@ -136,4 +136,10 @@ Disassembly of section .text:
 0+01f8 <[^>]*> 7d8b500a 	lwx	t2,t3\(t4\)
 0+01fc <[^>]*> 041cff80 	bposge32	00000000 <text_label>
 0+0200 <[^>]*> 00000000 	nop
+0+0204 <[^>]*> 716c1000 	madd	\$ac2,t3,t4
+0+0208 <[^>]*> 718d1801 	maddu	\$ac3,t4,t5
+0+020c <[^>]*> 71ae0004 	msub	t5,t6
+0+0210 <[^>]*> 71cf0805 	msubu	\$ac1,t6,t7
+0+0214 <[^>]*> 02b61818 	mult	\$ac3,s5,s6
+0+0218 <[^>]*> 02d70019 	multu	s6,s7
 	\.\.\.
Index: gas/mips/mips32-dsp.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips32-dsp.s,v
retrieving revision 1.2
diff -u -p -r1.2 mips32-dsp.s
--- gas/mips/mips32-dsp.s	5 Jun 2006 16:28:36 -0000	1.2
+++ gas/mips/mips32-dsp.s	21 Oct 2010 00:04:29 -0000
@@ -136,6 +136,12 @@ text_label:
 	lwx		$10,$11($12)
 	bposge32	text_label
 	nop
+	madd		$ac2,$11,$12
+	maddu		$ac3,$12,$13
+	msub		$ac0,$13,$14
+	msubu		$ac1,$14,$15
+	mult		$ac3,$21,$22
+	multu		$ac0,$22,$23
 
 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
 	.space	8


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