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Hi Richard,
It's been a while, but time has been spent well and here's the next
update to the code. I believe I have addressed all your concerns. Some
detailed notes follow below.
> > I have placed the translation in macro_map_reloc() now. That incurs an
> > O(n) performance penalty because all relocations in the microMIPS mode
> > have to be iterated over the table of mappings; regrettably BFD_RELOC_*
> > definitions are sparse so an O(1) lookup table cannot be used. By keeping
> > it sorted some time can be saved, but that's still O(n). This could be
> > reduced to O(log n) with a binary search, but I fear with the limited
> > number of relocs handled the overhead would kill the benefit.
>
> TBH, I think a case statement would be fine here. It's then up to
> the compiler to pick the best implementation.
Hmm, maybe, maybe not. Anyway my proposal is semantically correct, so if
you'd like to improve it, then please feel free. ;)
> > I have rewritten macro_end() entirely now. I have changed the approach
> > such that if multiple instructions are emitted into a branch delay slot
> > and the first of these instructions is out of size, then two warnings are
> > produced.
> >
> > The rationale is these are different classes of warnings -- the delay
> > slot size mismatch is fatal if the call is ever returned from. Multiple
> > instructions may or may not be a problem depending on the actual piece of
> > code and author's intentions. We had a discussion about it a few years
> > ago. ;)
> >
> > To complete these changes I have modified the change to append_insn()
> > such that no warning is produced for a delay slot size mismatch if called
> > for a macro expansion as it would get in the way, especially in the case
> > of relaxation. The API of this function had to be modified in a trivial
> > way and all the callers adjusted accordingly.
>
> I'll have to think about this a bit. And dig out that conversation ;-)
Have you?
> >> >> From a usability perspective, it's a shame that:
> >> >>
> >> >> .set micromips
> >> >> .ent foo
> >> >> foo:
> >> >> b 1f
> >> >> nop
> >> >> .end foo
> >> >> .ent bar
> >> >> bar:
> >> >> 1: nop
> >> >> .end bar
> >> >>
> >> >> disassembles as:
> >> >>
> >> >> 00000000 <foo>:
> >> >> 0: cfff b 0 <foo>
> >> >> 0: R_MICROMIPS_PC10_S1 .L11
> >> >> 2: 0c00 nop
> >> >> 4: 0c00 nop
> >> >>
> >> >> 00000006 <bar>:
> >> >> 6: 0c00 nop
> >> >>
> >> >> leaving the poor user with no idea what .L11 is.
> >> >
> >> > Indeed. This is a general limitation of `objdump' it would seem. This
> >> > is no different to what you get with:
> >> >
> >> > $ cat b.s
> >> > .globl baz
> >> > .ent foo
> >> > foo:
> >> > b baz
> >> > nop
> >> > .end foo
> >> > .ent bar
> >> > baz:
> >> > bar:
> >> > 1: nop
> >> > .end bar
> >> > $ mips-sde-elf-objdump -dr b.o
> >> >
> >> > b.o: file format elf32-tradbigmips
> >> >
> >> >
> >> > Disassembly of section .text:
> >> >
> >> > 00000000 <foo>:
> >> > 0: 1000ffff b 0 <foo>
> >> > 0: R_MIPS_PC16 baz
> >> > 4: 00000000 nop
> >> > 8: 00000000 nop
> >> >
> >> > 0000000c <bar>:
> >> > c: 00000000 nop
> >>
> >> Well, it's a little different. The user has at least defined two
> >> named symbols in this case, so they have a good chance of knowing
> >> what "baz" means. In the microMIPS case we've invented a label
> >> and are using it in preference to the user-defined one.
> >
> > That's unfortunate, indeed. [FIXME]
>
> Have you looked into the work involved, before this gets dismissed
> entirely as future work?
Well, first we'd have to come up with a solution before we go and think
about implementation. As it is I fail to see one -- please propose one
if you can think of any.
The thing is we really have to report the right symbol in the relocation.
Doing otherwise is the wrong thing to do as it's not the purpose of the
tool to add any interpretation beyond what the ELF standard provides and
will also confuse the user, especially when the replacement symbol chosen
with an .o file resolves to a different location on the final link.
Then we have no reliable way to report the generated symbol, especially
when --prefix-addresses is used.
We still have -t as a workaround.
> >> > I'd just recommend peeking at the symbol table (back to the first
> >> > program):
> >> >
> >> > $ mips-sde-elf-objdump -t b.o
> >> >
> >> > b.o: file format elf32-tradbigmips
> >> >
> >> > SYMBOL TABLE:
> >> > 00000000 l d .text 00000000 .text
> >> > 00000000 l d .data 00000000 .data
> >> > 00000000 l d .bss 00000000 .bss
> >> > 00000000 l d .reginfo 00000000 .reginfo
> >> > 00000000 l d .pdr 00000000 .pdr
> >> > 00000000 l F .text 00000006 0x80 foo
> >> > 00000006 l F .text 00000002 0x80 bar
> >> > 00000006 l .text 00000000 0x80 .L1^B1
> >>
> >> I suppose having a symbol with ^B in it is less than ideal too.
> >> AIUI that name was chosen specifically because it wasn't supposed
> >> to be written out.
> >>
> >> It would be especially confusing if the user or compiler had a ".L11"
> >> label (without the ^B).
> >
> > Actually this is a tough problem -- we need to emit a generated symbol
> > that does not clash with anything the user or GCC may have put in the
> > source. Any ideas? How is it done in other ports if anywhere?
>
> None off-hand. Seggestions from others very welcome.
>
> I'll try to think of something when I've got more time. For avoidance
> of doubt, I think this does need to be fixed.
While looking into it I have implemented Joseph's suggestion to cover all
these generated symbols with the --special-syms option. This has actually
revealed this is a preexisting problem as MIPS16 code already generates
such symbols (see the relevant test suite updates included with the patch;
search for --special-syms). While I do agree this is a problem that needs
to be addressed one way or another, given this circumstance I don't think
you can reasonably reject this submission on the basis of this problem
staying unfixed.
> >> @@ -14813,6 +16230,8 @@ mips_elf_final_processing (void)
> >> file_ase_mt is true. */
> >> if (file_ase_mips16)
> >> elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
> >> + if (file_ase_micromips)
> >> + elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS;
> >> #if 0 /* XXX FIXME */
> >> if (file_ase_mips3d)
> >> elf_elfheader (stdoutput)->e_flags |= ???;
> >>
> >> Do you really only want this flag to be set if -mmicromips was passed
> >> on the command line? (Yes, the same concern applies to MIPS16 and MDMX.)
> >
> > Fixing it up is easy, but I'm not sure what the original intent of these
> > flags has been. Do they mean:
> >
> > 1. I make use of the FOO feature and I assert it is available?
> >
> > 2. I make use of the FOO feature, but I may go and figure out if it's
> > available?
> >
> > 3. I make use of the FOO feature and want to prevent linking with any
> > incompatible ones?
> >
> > Once we've determined the answer we may modify code accordingly or leave
> > it as it is. It looks to me the current approach matches #1 and the ELF
> > program loader may refuse to execute the program if it sees a flag for a
> > feature that is not supported by the processor to run on. Any .set
> > fragments within the program are guarded appropriately and hence they do
> > not need to set the flag (as it would be for #2). Then #3 is sort of
> > tangential to the two others, but it does matter in this context, hence I
> > mentioned it (i.e. if #3 was true, then I'd be much happier with #3 & #1
> > than #3 & #2; otherwise I don't have a strong preference between #1 and
> > #2).
> >
> > Current arrangement is similar to that of file_mips_isa even though the
> > ISA can be overridden by .set too and I think it makes sense to keep all
> > these flags consistent.
>
> I think MIPS16 and microMIPS are fundamentally different from the ISA,
> and even from MDMX. IMO, it's reasonable to assume that, if the user is
> taking a MIPS III target as their base system, that they'll assemble
> with a MIPS III ISA flag. I know others disagree, and think that such
> things should always be specified by pseudo-ops. Even if you're of that
> opinion, though, it's easy in principle to set the flags to the minimum
> ISA required by the assembly source.
>
> MIPS16 and microMIPS are different because they represent an operating
> mode that the processor can switch in and out of. The fact that the
> assembly source contains both MIPS16 and non-MIPS16 code isn't really a
> good indicator that the code is designed to cope with non-MIPS16-capable
> systems.
>
> We could live without deciding between #1, #2 and #3 until now because
> MIPS16 was the only feature like this. Now that we've got two
> incompatible code-compression methods, I think it's more important.
>
> I too would like to hear other opinions. I'm just not convinced by
> the "it's similar to ISA selection" argument. More below.
Have you, actually? See below too.
> >> micromips_ip obviously started life as a cut-&-paste of mips_ip, and it
> >> would have been nice to factor some code out. At least split out the
> >> block beginning:
> >>
> >> + case 'F':
> >> + case 'L':
> >> + case 'f':
> >> + case 'l':
> >> + {
> >>
> >> which is identical between the two, and far too subtle to copy wholesale.
> >> There may be other good opportunities too.
> >
> > Next time, I'm afraid. [FIXME]
>
> Next time == next iteration? If so, that's fine, but I think this
> has to be fixed for the patch to be acceptable.
I have folded micromips_ip() into mips_ip() now. This revealed a couple
of preexisting problems that I fixed with some of the patches sent
previously. Likewise fixes for problems with new microMIPS code have been
included here.
> >> The same cut-&-paste concerns apply to micromips_macro, which obviously
> >> started out as a copy of macro(). I realise there are special cases
> >> for micromips (such as the DADDI assymmetry and the lack of
> >> branch-likely instructions, to name only a few), but most of the
> >> basic decisions are the same.
> >>
> >> As it stands, we have a new 3524 line function, of which I imagine at
> >> least 90% is shared with macro(). I really think the new microMIPS
> >> macro handling should be integrated into macro() instead. Don't be
> >> afraid of factoring out code from macro() if it makes it easier to
> >> integrate the microMIPS code.
> >
> > Can we make it a follow-up patch sometime in the future? I'm not afraid
> > of factoring code out of anywhere (I'm speaking of myself only of course),
> > but at this point the effort is about the same as writing this whole stuff
> > from scratch. :( [FIXME]
>
> Sorry, I know it's a pain, but I just don't think the patch can go
> in as it stands. The fact that the amount of work is so daunting
> means that (even with the best of intentions, which I realise yours
> are), that follow-up is unlikely to happen. In the meantime we'll
> have a 3524-line function (haven't recalculated ;-)) that has to be
> kept in sync with another even bigger function (or pair of functions),
> and it just won't be obvious whether the divergences are deliberate
> microMIPS differences or whether they're cases where the two functions
> haven't been updated in the same way.
>
> I remember how painful it was replacing the old macro relaxation
> code so that it could support arbitrary alternatives. This sort
> of thing would double that pain.
>
> And it's not just (or even principally) about cut-&-paste phobia.
> microMIPS has been deliberately designed to provide a great deal
> of source-level backwards compatibility, so it's no surprise that
> the two modes require very similar code, and very similar decisions.
> I think having a single function handling both is actually significantly
> clearer, because it calls out which differences are deliberate,
> hopefully with a helpful bit of commentary where necessary.
>
> As things stand, it's already a bit of an archaeology exercise trying
> to decide what the differences actually are.
Likewise, I have folded micromips_macro() into macro() and as a bonus
micromips_macro_build() into macro_build() as well. Again, this revealed
numerous problems that I fixed too.
> > Overall I'm a bit concerned about all this linker relaxation stuff -- it
> > breaks -falign-jumps, -falign-labels and -falign-loops which may have a
> > severe performance penalty and should therefore be enabled conditionally
> > only, preferably where all the three options are set to 1 (meaning that
> > would be naturally implied by -Os). A linker option would be required an
> > set appropriately by the GCC driver. [FIXME]
>
> Yeah, I agree a bit more rigour would be nice here. Without it, though,
> I think it's generally OK to assume that anyone using MIPS16 or microMIPS
> is more of the -Os rather than -O2 mindset, so I agree this is at most a
> FIXME.
Mindset aside, GCC has a documented behaviour that does not include
"maybe" in its definition. It might make sense to update GCC
documentation to warn the user at the very least.
> >> Did you actually test this with n64, say with a gcc bootstrap? Same
> >> comment goes for elfn32-mips.c.
> >>
> >> Why only do the linker relaxation for elf32-mips.c (o32, o64 & EABI)?
> >> Why not for n32 and n64 too?
> >
> > The answer to all the questions is negative. There is no 64-bit
> > microMIPS hardware available at the moment. The best bet might be QEMU --
> > NathanF, have you implemented any of the 64-bit instructions in QEMU?
> > Otherwise there's probably no way do do any of 64-bit microMIPS testing
> > beside what's done in binutils. And no library work of any kind has
> > started for 64-bit microMIPS support AFAIK. Hence there has been little
> > incentive to attempt anything but rudimentary support for 64-bit ABIs.
>
> OK, in that case, never mind about testing 64-bit ;-) However...
>
> > I envisage all the relaxation stuff to be either moved over to
> > elfxx-mips.c or copied to elfn32-mips.c and elf64-mips.c, as applicable,
> > once we have real 64-bit support.
>
> ...I still think this stuff should start life in elfxx-mips.c, even if
> it's only used by elf32-mips.c at first.
I have moved this piece now then, although care has to be taken about it
-- there are some assumptions about o32 hardcoded, e.g. the HI16/LO16
relaxation is certainly dangerous on n64 and may lead to broken code
(ADDIUPC has undefined semantics outside compatibility segments).
> >> @@ -5127,12 +5200,26 @@ mips_elf_calculate_relocation (bfd *abfd
> >> + h->la25_stub->stub_section->output_offset
> >> + h->la25_stub->offset);
> >>
> >> + /* Make sure MIPS16 and microMIPS are not used together. */
> >> + if ((r_type == R_MIPS16_26 && target_is_micromips_code_p)
> >> + || (r_type == R_MICROMIPS_26_S1 && target_is_16_bit_code_p))
> >> + {
> >> + (*_bfd_error_handler)
> >> + (_("MIPS16 and microMIPS functions cannot call each other"));
> >> + return bfd_reloc_notsupported;
> >> + }
> >>
> >> Should this be extended to check for branches too?
> >
> > That would be a useful improvement I suppose, but MIPS16 code doesn't
> > care either (you can't use a branch to switch the ISA mode). Overall I
> > think it's a corner case -- branches to external symbols are a rarity.
> > [FIXME]
>
> But it is (or feels like) something that people have asked about on many
> occasions, before we decided to ignore the botched ABI definition of
> R_MIPS_PC16.
>
> If it was a lot of work, I'd be sympathetic, but I think this is
> something that's easily done, and handling one pair of relocs without
> the others seems inconsistent.
Fixed, thanks for your point.
> >> - /* If this is an odd-valued function symbol, assume it's a MIPS16 one. */
> >> + /* If this is an odd-valued function symbol, assume it's a MIPS16
> >> + or microMIPS one. */
> >> if (ELF_ST_TYPE (elfsym->internal_elf_sym.st_info) == STT_FUNC
> >> && (asym->value & 1) != 0)
> >> {
> >> asym->value--;
> >> - elfsym->internal_elf_sym.st_other
> >> - = ELF_ST_SET_MIPS16 (elfsym->internal_elf_sym.st_other);
> >> + if (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS)
> >> + elfsym->internal_elf_sym.st_other
> >> + = ELF_ST_SET_MICROMIPS (elfsym->internal_elf_sym.st_other);
> >> + else
> >> + elfsym->internal_elf_sym.st_other
> >> + = ELF_ST_SET_MIPS16 (elfsym->internal_elf_sym.st_other);
> >> }
> >> }
> >>
> >>
> >> So a file can't mix MIPS16 and microMIPS code? We should probably
> >> detect that explicitly. I'd like a clear statement of what the
> >> interoperability restrictions are.
> >>
> >> This goes back to the question of when EF_MIPS_ARCH_ASE_MICROMIPS
> >> should be set (see previous reviews).
> >
> > Background information first -- you can't have a piece of MIPS hardware,
> > either real or simulated, with the MIPS16 ASE and the microMIPS ASE
> > implemented both at a time. This is a design assumption that allowed the
> > ISA bit to be overloaded.
> >
> > That obviously does not mean -- in principle -- that you can't have an
> > executable (or one plus a mixture of shared libraries) where some
> > functions are MIPS16 code and some are microMIPS code, either of which
> > only called once the presence of the respective ASE has been determined.
> > While a valid configuration this is also a rare exotic corner case -- I
> > could imagine a piece of generic, processor-independent console/bootstrap
> > firmware like this for example, but little beyond that.
> >
> > We had a discussion about it and the conclusion was from the user's
> > perspective the most beneficial configuration is one where mixing MIPS16
> > and microMIPS code within a single executable is forbidden by default.
> > The reason is a build-time error is always better than a run-time one
> > (especially when the device has been placed out there in the field
> > already; hopefully not an Ariane 5 rocket) and the case where mixing
> > MIPS16 and microMIPS code would almost always happen is when the user
> > picked the wrong library by mistake. It is therefore most productive to
> > fail at this point rather than later.
>
> I agree. In that case, though, I think it's important that we go for #1
> in your list above, otherwise this check doesn't really count for much.
> I think having a way of forcing interpretation #2 fits into the same
> category as...
So I have changed the semantics of both flags now -- either of these is
only ever set if actual MIPS16 or microMIPS code have been generated.
Data does not count and neither does either the -mips16/-mmicromips option
or the .set mips16/micromips pseudo-op. Linking modules containing MIPS16
code together with ones containing microMIPS code has been forbidden. I
have added an LD test case to verify that.
> > A future enhancement could add assembler and linker switches to override
> > this default and mix the two ASEs in a single executable. [FIXME]
>
> ...this, which I agree is best left for future work.
So I did.
Beside the above I have made numerous bug fixes and applied less critical
clean-ups throughout the code. Tested as usually, with mips-sde-elf and
mips-linux-gnu. But I enabled NewABI tests this time too and (trivially)
adjusted the relevant test case matching patterns, i.e. there should be no
failures induced by the addition of microMIPS support with targets like
mips64*-linux-gnu either.
Maciej
binutils-20101207-umips.diff
[Patch attached compressed due to its size.]
bfd/
2010-12-07 Chao-ying Fu <fu@mips.com>
Ilie Garbacea <ilie@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Catherine Moore <clm@codesourcery.com>
* archures.c (bfd_mach_mips_micromips): New macro.
* cpu-mips.c (I_micromips): New enum value.
(arch_info_struct): Add bfd_mach_mips_micromips.
* elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New
prototype.
(_bfd_mips_elf_relax_section): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(gprel16_reloc_p): Handle microMIPS ASE.
(literal_reloc_p): New function.
* elf32-mips.c (elf_micromips_howto_table_rel): New variable.
(_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(mips_elf_gprel32_reloc): Update comment.
(micromips_reloc_map): New variable.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(mips_elf32_rtype_to_howto): Likewise.
(mips_info_to_howto_rel): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
(bfd_elf32_bfd_relax_section): Likewise.
* elf64-mips.c (micromips_elf64_howto_table_rel): New variable.
(micromips_elf64_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf64_bfd_reloc_name_lookup): Likewise.
(mips_elf64_rtype_to_howto): Likewise.
(bfd_elf64_bfd_is_target_special_symbol): Define.
* elfn32-mips.c (elf_micromips_howto_table_rel): New variable.
(elf_micromips_howto_table_rela): Likewise.
(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
and _bfd_mips_elf_reloc_shuffle changes.
(micromips_reloc_map): Likewise.
(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
(bfd_elf32_bfd_reloc_name_lookup): Likewise.
(mips_elf_n32_rtype_to_howto): Likewise.
(bfd_elf32_bfd_is_target_special_symbol): Define.
* elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro.
(LA25_LUI_MICROMIPS_2): Likewise.
(LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise.
(LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise.
(TLS_RELOC_P): Handle microMIPS ASE.
(mips_elf_create_stub_symbol): Adjust value of stub symbol if
target is a microMIPS function.
(micromips_reloc_p): New function.
(micromips_reloc_shuffle_p): Likewise.
(got16_reloc_p, call16_reloc_p): Handle microMIPS ASE.
(got_disp_reloc_p, got_page_reloc_p): New functions.
(got_ofst_reloc_p): Likewise.
(got_hi16_reloc_p, got_lo16_reloc_p): Likewise.
(call_hi16_reloc_p, call_lo16_reloc_p): Likewise.
(hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE.
(micromips_branch_reloc_p): New function.
(tls_gd_reloc_p, tls_ldm_reloc_p): Likewise.
(tls_gottprel_reloc_p): Likewise.
(_bfd_mips16_elf_reloc_unshuffle): Rename to...
(_bfd_mips_elf_reloc_unshuffle): ... this. Handle microMIPS
ASE.
(_bfd_mips16_elf_reloc_shuffle): Rename to...
(_bfd_mips_elf_reloc_shuffle): ... this. Handle microMIPS ASE.
(_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE.
(mips_tls_got_index, mips_elf_got_page): Likewise.
(mips_elf_create_local_got_entry): Likewise.
(mips_elf_relocation_needs_la25_stub): Likewise.
(mips_elf_calculate_relocation): Likewise.
(mips_elf_perform_relocation): Likewise.
(_bfd_mips_elf_symbol_processing): Likewise.
(_bfd_mips_elf_add_symbol_hook): Likewise.
(_bfd_mips_elf_link_output_symbol_hook): Likewise.
(mips_elf_add_lo16_rel_addend): Likewise.
(_bfd_mips_elf_check_relocs): Likewise.
(mips_elf_adjust_addend): Likewise.
(_bfd_mips_elf_relocate_section): Likewise.
(mips_elf_create_la25_stub): Likewise.
(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
(_bfd_mips_elf_gc_sweep_hook): Likewise.
(_bfd_mips_elf_is_target_special_symbol): New function.
(mips_elf_relax_delete_bytes): Likewise.
(opcode_descriptor): New structure.
(RA): New macro.
(OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise.
(b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables.
(beq_insn_32): Likewise.
(b_insn_16, bz_insn_16): New variables.
(BZ32_REG, BZ32_REG_FIELD): New macros.
(bz_insns_32, bzc_insns_32, bz_insns_16): New variables.
(BZ16_REG, BZ16_REG_FIELD): New macros.
(jal_insn_32_bd16, jal_insn_32_bd32): New variables.
(j_insn_32, jalr_insn_32): Likewise.
(JALR_SREG, JALR_TREG): New macros.
(call_insn_32_bd16, call_insn_32_bd32): New variables.
(ds_insns_32_bd16): Likewise.
(jalx_insn_32_bd32): Likewise.
(jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise.
(JR16_REG): New macro.
(ds_insns_16_bd16): New variable.
(lui_insn): Likewise.
(addiu_insn, addiupc_insn): Likewise.
(ADDIUPC_REG_FIELD): New macro.
(MOVE32_RD, MOVE32_RS): Likewise.
(MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise.
(move_insns_32, move_insns_16): New variables.
(nop_insn_32, nop_insn_16): Likewise.
(MATCH): New macro.
(find_match): New function.
(relax_dslot_norel16, relax_dslot_norel32): Likewise.
(relax_dslot_rel): Likewise.
(IS_BITSIZE): New macro.
(_bfd_mips_elf_relax_section): New function.
(_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16
and microMIPS modules together.
(_bfd_mips_elf_print_private_bfd_data): Handle microMIPS ASE.
* reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation.
(BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise.
(BFD_RELOC_MICROMIPS_GPREL16): Likewise.
(BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise.
(BFD_RELOC_MICROMIPS_HI16_S): Likewise.
(BFD_RELOC_MICROMIPS_LO16): Likewise.
(BFD_RELOC_MICROMIPS_LITERAL): Likewise.
(BFD_RELOC_MICROMIPS_GOT16): Likewise.
(BFD_RELOC_MICROMIPS_CALL16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_HI16): Likewise.
(BFD_RELOC_MICROMIPS_GOT_LO16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_CALL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_SUB): Likewise.
(BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise.
(BFD_RELOC_MICROMIPS_GOT_OFST): Likewise.
(BFD_RELOC_MICROMIPS_GOT_DISP): Likewise.
(BFD_RELOC_MICROMIPS_HIGHEST): Likewise.
(BFD_RELOC_MICROMIPS_HIGHER): Likewise.
(BFD_RELOC_MICROMIPS_SCN_DISP): Likewise.
(BFD_RELOC_MICROMIPS_JALR): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GD): Likewise.
(BFD_RELOC_MICROMIPS_TLS_LDM): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise.
(BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
binutils/
2010-12-07 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* readelf.c (get_machine_flags): Handle microMIPS ASE.
(get_mips_symbol_other): Likewise.
gas/
2010-12-07 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* config/tc-mips.h (mips_segment_info): Add one bit for
microMIPS.
(TC_LABEL_IS_LOCAL): New macro.
(mips_label_is_local): New prototype.
* config/tc-mips.c (emit_branch_likely_macro): New variable.
(mips_set_options): Add micromips.
(mips_opts): Initialise micromips to -1.
(file_ase_micromips): New variable.
(CPU_HAS_MICROMIPS): New macro.
(hilo_interlocks): Set for microMIPS too.
(gpr_interlocks): Likewise.
(cop_interlocks): Likewise.
(cop_mem_interlocks): Likewise.
(HAVE_CODE_COMPRESSION): New macro.
(micromips_op_hash): New variable.
(micromips_nop16_insn, micromips_nop32_insn): New variables.
(NOP_INSN): Handle microMIPS ASE.
(mips32_to_micromips_reg_b_map): New macro.
(mips32_to_micromips_reg_c_map): Likewise.
(mips32_to_micromips_reg_d_map): Likewise.
(mips32_to_micromips_reg_e_map): Likewise.
(mips32_to_micromips_reg_f_map): Likewise.
(mips32_to_micromips_reg_g_map): Likewise.
(mips32_to_micromips_reg_l_map): Likewise.
(mips32_to_micromips_reg_n_map): Likewise.
(mips32_to_micromips_reg_h_map): New variable.
(mips32_to_micromips_reg_m_map): Likewise.
(mips32_to_micromips_reg_q_map): Likewise.
(micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_to_32_reg_b_map): New macro.
(micromips_to_32_reg_c_map): Likewise.
(micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map): Likewise.
(micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map): Likewise.
(micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_n_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): New macros.
(RELAX_DELAY_SLOT_16BIT): New macro.
(RELAX_DELAY_SLOT_SIZE_FIRST): Likewise.
(RELAX_DELAY_SLOT_SIZE_SECOND): Likewise.
(RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros.
(RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_USER_16BIT): Likewise.
(RELAX_MICROMIPS_UNCOND, RELAX_MICROMIPS_LINK): Likewise.
(RELAX_MICROMIPS_TOOFAR, RELAX_MICROMIPS_MARK_TOOFAR): Likewise.
(RELAX_MICROMIPS_CLEAR_TOOFAR): Likewise.
(RELAX_MICROMIPS_EXTENDED): Likewise.
(RELAX_MICROMIPS_MARK_EXTENDED): Likewise.
(RELAX_MICROMIPS_CLEAR_EXTENDED): Likewise.
(INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE.
(mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p,
fsize and insns.
(mips_mark_labels): New function.
(mips16_small, mips16_ext): Remove variables, replacing with...
(forced_insn_size): ... this.
(append_insn, mips16_ip): Update accordingly.
(micromips_insn_length): New function.
(insn_length): Return the length of microMIPS instructions.
(mips_record_mips16_mode): Rename to...
(mips_record_compressed_mode): ... this. Handle microMIPS ASE.
(install_insn): Handle microMIPS ASE.
(is_size_valid, is_delay_slot_valid): New functions.
(md_begin): Handle microMIPS ASE.
(md_assemble): Likewise. Update for append_insn interface
change.
(micromips_reloc_p): New function.
(got16_reloc_p): Handle microMIPS ASE.
(hi16_reloc_p): Likewise.
(lo16_reloc_p): Likewise.
(matching_lo_reloc): Likewise.
(insn_uses_reg, reg_needs_delay): Likewise.
(mips_move_labels): Likewise.
(mips16_mark_labels): Rename to...
(mips_compressed_mark_labels): ... this. Handle microMIPS ASE.
(insns_between, nops_for_vr4130, nops_for_insn): Likewise.
(fix_loongson2f_nop, fix_loongson2f_jump): Likewise.
(MICROMIPS_LABEL_CHAR): New macro.
(micromips_target_label, micromips_target_name): New variables.
(micromips_label_name, micromips_label_expr): New functions.
(micromips_label_inc, micromips_add_label): Likewise.
(mips_label_is_local): Likewise.
(append_insn): Add expansionp argument. Handle microMIPS ASE.
(start_noreorder, end_noreorder): Handle microMIPS ASE.
(macro_start, macro_warning, macro_end): Likewise.
(brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables.
(mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise.
(BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros.
(MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise.
(macro_map_reloc): New function.
(macro_build): Handle microMIPS ASE. Update for append_insn
interface change.
(mips16_macro_build): Update for append_insn interface change.
(macro_build_jalr): Handle microMIPS ASE.
(macro_build_lui): Likewise. Simplify.
(load_register): Handle microMIPS ASE.
(load_address): Likewise.
(move_register): Likewise.
(macro_build_branch_likely): New function.
(macro_build_branch_ccl): Likewise.
(macro_build_branch_rs): Likewise.
(macro_build_branch_rsrt): Likewise.
(macro): Handle microMIPS ASE.
(validate_micromips_insn): New function.
(SKIP_SPACE_TABS): Move earlier on.
(mips_ip): Handle microMIPS ASE.
(micromips_percent_op): New variable.
(parse_relocation): Handle microMIPS ASE.
(my_getExpression): Likewise.
(options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS.
(md_longopts): Add mmicromips and mno-micromips.
(md_parse_option): Handle OPTION_MICROMIPS and
OPTION_NO_MICROMIPS.
(mips_after_parse_args): Handle microMIPS ASE.
(md_pcrel_from): Handle microMIPS relocations.
(mips_force_relocation): Likewise.
(md_apply_fix): Likewise.
(mips_align): Handle microMIPS ASE.
(s_mipsset): Likewise.
(s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers.
(s_dtprel_internal): Likewise.
(s_gpword, s_gpdword): Likewise.
(s_insn): Handle microMIPS ASE.
(s_mips_stab): Likewise.
(relaxed_micromips_32bit_branch_length): New function.
(relaxed_micromips_16bit_branch_length): New function.
(md_estimate_size_before_relax): Handle microMIPS ASE.
(mips_fix_adjustable): Likewise.
(tc_gen_reloc): Handle microMIPS relocations.
(mips_relax_frag): Handle microMIPS ASE.
(md_convert_frag): Likewise.
(mips_frob_file_after_relocs): Likewise.
(mips_elf_final_processing): Likewise.
(mips_nop_opcode): Likewise.
(mips_handle_align): Likewise.
(md_show_usage): Handle microMIPS options.
* symbols.c (TC_LABEL_IS_LOCAL): New macro.
(S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check.
* doc/as.texinfo (Target MIPS options): Add -mmicromips and
-mno-micromips.
(-mmicromips, -mno-micromips): New options.
* doc/c-mips.texi (-mmicromips, -mno-micromips): New options.
(MIPS ISA): Document .set micromips and .set nomicromips.
(MIPS insn): Update for microMIPS support.
gas/testsuite/
2010-12-07 Maciej W. Rozycki <macro@codesourcery.com>
Chao-ying Fu <fu@mips.com>
* gas/mips/micromips.d: New test.
* gas/mips/micromips-branch-delay.d: Likewise.
* gas/mips/micromips-branch-relax.d: Likewise.
* gas/mips/micromips-branch-relax-pic.d: Likewise.
* gas/mips/micromips-size-1.d: Likewise.
* gas/mips/micromips-trap.d: Likewise.
* gas/mips/micromips.l: New stderr output.
* gas/mips/micromips-branch-delay.l: Likewise.
* gas/mips/micromips-branch-relax.l: Likewise.
* gas/mips/micromips-branch-relax-pic.l: Likewise.
* gas/mips/micromips-size-0.l: New list test.
* gas/mips/micromips-size-1.l: New stderr output.
* gas/mips/micromips.s: New test source.
* gas/mips/micromips-branch-delay.s: Likewise.
* gas/mips/micromips-branch-relax.s: Likewise.
* gas/mips/micromips-size-0.s: Likewise.
* gas/mips/micromips-size-1.s: Likewise.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/elf_ase_micromips.d: New test.
* gas/mips/elf_ase_micromips-1.d: Likewise.
* gas/mips/micromips@abs.d: Likewise.
* gas/mips/micromips@add.d: Likewise.
* gas/mips/micromips@and.d: Likewise.
* gas/mips/micromips@beq.d: Likewise.
* gas/mips/micromips@bge.d: Likewise.
* gas/mips/micromips@bgeu.d: Likewise.
* gas/mips/micromips@blt.d: Likewise.
* gas/mips/micromips@bltu.d: Likewise.
* gas/mips/micromips@branch-likely.d: Likewise.
* gas/mips/micromips@branch-misc-1.d: Likewise.
* gas/mips/micromips@branch-misc-2-64.d: Likewise.
* gas/mips/micromips@branch-misc-2.d: Likewise.
* gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
* gas/mips/micromips@branch-misc-2pic.d: Likewise.
* gas/mips/micromips@branch-self.d: Likewise.
* gas/mips/micromips@dli.d: Likewise.
* gas/mips/micromips@elf-jal.d: Likewise.
* gas/mips/micromips@elf-rel2.d: Likewise.
* gas/mips/micromips@elf-rel4.d: Likewise.
* gas/mips/micromips@jal-svr4pic.d: Likewise.
* gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise.
* gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise.
* gas/mips/micromips@li.d: Likewise.
* gas/mips/micromips@mips1-fp.d: Likewise.
* gas/mips/micromips@mips32-cp2.d: Likewise.
* gas/mips/micromips@mips32-imm.d: Likewise.
* gas/mips/micromips@mips32-sf32.d: Likewise.
* gas/mips/micromips@mips32.d: Likewise.
* gas/mips/micromips@mips32r2-cp2.d: Likewise.
* gas/mips/micromips@mips32r2-fp32.d: Likewise.
* gas/mips/micromips@mips32r2.d: Likewise.
* gas/mips/micromips@mips4-branch-likely.d: Likewise.
* gas/mips/micromips@mips4-fp.d: Likewise.
* gas/mips/micromips@mips4.d: Likewise.
* gas/mips/micromips@mips5.d: Likewise.
* gas/mips/micromips@mips64-cp2.d: Likewise.
* gas/mips/micromips@mips64.d: Likewise.
* gas/mips/micromips@mips64r2.d: Likewise.
* gas/mips/micromips@rol-hw.d: Likewise.
* gas/mips/micromips@uld2-eb.d: Likewise.
* gas/mips/micromips@uld2-el.d: Likewise.
* gas/mips/micromips@ulh2-eb.d: Likewise.
* gas/mips/micromips@ulh2-el.d: Likewise.
* gas/mips/micromips@ulw2-eb-ilocks.d: Likewise.
* gas/mips/micromips@ulw2-el-ilocks.d: Likewise.
* gas/mips/mips32-imm.d: Likewise.
* gas/mips/elf-rel27.d: Handle microMIPS ASE.
* gas/mips/l_d.d: Likewise.
* gas/mips/l_d-n32.d: Likewise.
* gas/mips/l_d-n64.d: Likewise.
* gas/mips/ld.d: Likewise.
* gas/mips/ld-n32.d: Likewise.
* gas/mips/ld-n64.d: Likewise.
* gas/mips/s_d.d: Likewise.
* gas/mips/s_d-n32.d: Likewise.
* gas/mips/s_d-n64.d: Likewise.
* gas/mips/sd.d: Likewise.
* gas/mips/sd-n32.d: Likewise.
* gas/mips/sd-n64.d: Likewise.
* gas/mips/mips32.d: Update immediates.
* gas/mips/micromips@mips32-cp2.s: New test source.
* gas/mips/micromips@mips32-imm.s: Likewise.
* gas/mips/micromips@mips32r2-cp2.s: Likewise.
* gas/mips/micromips@mips64-cp2.s: Likewise.
* gas/mips/mips32-imm.s: Likewise.
* gas/mips/elf-rel4.s: Handle microMIPS ASE.
* gas/mips/lb-pic.s: Likewise.
* gas/mips/ld.s: Likewise.
* gas/mips/mips32.s: Likewise.
* gas/mips/mips.exp: Add the micromips arch. Exclude mips16e
from micromips. Run mips32-imm.
* gas/mips/jal-mask-11.d: New test.
* gas/mips/jal-mask-12.d: Likewise.
* gas/mips/micromips@jal-mask-11.d: Likewise.
* gas/mips/jal-mask-1.s: Source for the new tests.
* gas/mips/jal-mask-21.d: New test.
* gas/mips/jal-mask-22.d: Likewise.
* gas/mips/micromips@jal-mask-12.d: Likewise.
* gas/mips/jal-mask-2.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.
* gas/mips/mips16-e.d: Add --special-syms to `objdump'.
* gas/mips/tmips16-e.d: Likewise.
* gas/mips/and.s: Adjust padding.
* gas/mips/beq.s: Likewise.
* gas/mips/bge.s: Likewise.
* gas/mips/bgeu.s: Likewise.
* gas/mips/blt.s: Likewise.
* gas/mips/bltu.s: Likewise.
* gas/mips/branch-misc-2.s: Likewise.
* gas/mips/jal.s: Likewise.
* gas/mips/li.s: Likewise.
* gas/mips/mips1-fp.s: Likewise.
* gas/mips/mips32r2-fp32.s: Likewise.
* gas/mips/mips64.s: Likewise.
* gas/mips/mips4.s: Likewise.
* gas/mips/mips4-fp.s: Likewise.
* gas/mips/and.d: Update accordingly.
* gas/mips/elf-jal.d: Likewise.
* gas/mips/jal.d: Likewise.
* gas/mips/li.d: Likewise.
* gas/mips/mips1-fp.d: Likewise.
* gas/mips/mips32r2-fp32.d: Likewise.
* gas/mips/mips64.d: Likewise.
include/elf/
2010-12-07 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (R_MICROMIPS_min): New relocations.
(R_MICROMIPS_26_S1): Likewise.
(R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
(R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
(R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
(R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
(R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
(R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
(R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
(R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
(R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
(R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
(R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
(R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
(R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
(R_MICROMIPS_TLS_GOTTPREL): Likewise.
(R_MICROMIPS_TLS_TPREL_HI16): Likewise.
(R_MICROMIPS_TLS_TPREL_LO16): Likewise.
(R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
(R_MICROMIPS_max): Likewise.
(EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
(STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
(ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
(STO_MICROMIPS): Likewise.
(ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
(ELF_ST_IS_COMPRESSED): Likewise.
(STO_MIPS_PLT, STO_MIPS_PIC): Rework.
(ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
(STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.
include/opcode/
2010-12-07 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
(OP_MASK_RS3, OP_SH_RS3): Likewise.
(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): New macros.
(INSN2_WRITE_GPR_S, INSN2_READ_FPR_D): Likewise.
(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC, INSN2_MOD_GPR_MD): Likewise.
(INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
(INSN2_MOD_SP, INSN2_READ_GPR_31): Likewise.
(INSN2_READ_GP, INSN2_READ_PC): Likewise.
(CPU_MICROMIPS): New macro.
(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL, M_BEQL, M_BGEZL): New enum
values.
(M_BGEZALL, M_BGTZL, M_BLEZL, M_BLTZL, M_BLTZALL): Likewise.
(M_CACHE_OB, M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWP_AB, M_LWP_OB): Likewise.
(M_LWR_OB, M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB, M_SDP_AB): Likewise.
(M_SDP_OB, M_SDR_OB, M_SWC2_OB, M_SWL_OB, M_SWM_AB): Likewise.
(M_SWM_OB, M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
(micromips_opcodes): New declaration.
(bfd_micromips_num_opcodes): Likewise.
* mips.h (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): New macros.
* mips.h (INSN2_MOD_GPR_MHI): New macro.
(INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
ld/testsuite/
2010-12-07 Catherine Moore <clm@codesourcery.com>
Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* lib/ld-lib.exp (run_dump_test): Support distinct assembler
flags for the same source named multiple times.
* ld-mips-elf/jalx-1.s: New test source.
* ld-mips-elf/jalx-1.d: New test output.
* ld-mips-elf/jalx-1.ld: New test linker script.
* ld-mips-elf/jalx-2-main.s: New test source.
* ld-mips-elf/jalx-2-ex.s: Likewise.
* ld-mips-elf/jalx-2-printf.s: Likewise.
* ld-mips-elf/jalx-2.dd: New test output.
* ld-mips-elf/jalx-2.ld: New test linker script.
* ld-mips-elf/mips16-and-micromips.d: New test.
* ld-mips-elf/mips-elf.exp: Run the new tests
opcodes/
2010-12-07 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c: New file.
* mips-dis.c (micromips_to_32_reg_b_map): New array.
(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
(micromips_to_32_reg_q_map): Likewise.
(micromips_imm_b_map, micromips_imm_c_map): Likewise.
(micromips_ase): New variable.
(is_micromips): New function.
(set_default_mips_dis_options): Handle microMIPS ASE.
(print_insn_micromips): New function.
(is_compressed_mode_p): Likewise.
(_print_insn_mips): Handle microMIPS instructions.
* Makefile.am (CFILES): Add micromips-opc.c.
* configure.in (bfd_mips_arch): Add micromips-opc.lo.
* Makefile.in: Regenerate.
* configure: Regenerate.
* mips-dis.c (micromips_to_32_reg_h_map): New variable.
(micromips_to_32_reg_i_map): Likewise.
(micromips_to_32_reg_m_map): Likewise.
(micromips_to_32_reg_n_map): New macro.Attachment:
binutils-20101207-umips.diff.bz2
Description: Binary data
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