Hi,
While working on the microMIPS change I have stumbled across the GAS hack
to support ISA subsetting for the Octeon processors, used to exclude some
of the CP0 operations. I decided to implement this properly, based on my
previous experiments in this area.
Here's my proposal. It adds an "exclusions" field to the mips_opcode
structure. The new field defines a set of CPU membership flags to exclude
an opcode for just like they are used with the "membership" field,
overriding the membership information in the latter field. Currently only
CPU_OCTEON has been made to work like this and flags may be added in the
future as a need arises. An ISA flag could be handled in a similar way,
although one is unlikely to be ever needed here.
The advantage of this approach compared to the current one is not only
GAS correctly excludes the unsupported opcodes, but `objdump' does as
well. And it scales easily, requiring no changes outside opcodes.
Finally, it makes it clear which opcodes are really unsupported on Octeon
-- with the current approach it is a bit buried down within code.
As I've thought adding a trailing zero to initialise the new field
explicitly throughout the opcode tables would be unnecessary obfuscation
I've decided to initialise it to a non-zero value for opcodes that require
it only and allow the source files defining the MIPS opcode tables to have
uninitialised structure members with the -Wno-missing-field-initializers
GCC option. I think it is a good compromise -- these tables are validated
at run time too and the files contain no other code.
I have decided to retain the CP pinfo flag defined with the change that
introduced the current Octeon opcode exclusion code. The flag is not used
anymore, but the effort previously taken to annotate the relevant opcodes
may be useful for something else in the future.
No regressions for mips-sde-elf nor mips-linux-gnu. Applies on top of
the microMIPS change.