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Re: [ARM] signed zero
On Tue, 24 May 2011, Matthew Gretton-Dann wrote:
> > > Looking at the source code and tests I think I agree with most of the
> > > times you elide +0. However, you seem to elide the offset when doing a
> > > literal load (for instance ldr r0, [pc, #0] is being disassembled as ldr
> > > r0, [pc]). In this case I think the offset should be shown, and this is
> > > also what the ARMARM does (see section A8.6.59 for example).
> >
> > I think those bits were Maciej's changes, for consistency with displaying the
> > same addressing mode with other base registers. I'm not sure which version of
> > the ARM ARM you're looking at -- the one I have (ARM DDI 0100I) doesn't have a
> > section A8.
>
> I'm looking at the v7-AR ARMARM (ARM DDI 0406B) - this is available on
> the ARM documentation website (http://infocenter.arm.com/).
I have a vague recollection of sorting these bits out while merging
conflicting versions of upstream and our code base. It's been a while, so
I'd have do dig out the details, but my understanding is you find the
presence of the insignificant zero immediate offset in disassembly
important in the specific case of the PC or r15 being used as the base
register (as opposed to where one of the other registers is used as the
base). Would you please elaborate why this is the case?
In particular given the following source:
$ cat ldr.s
ldr r0, [pc, #0]
ldr r0, [pc]
ldr r0, [r1, #0]
ldr r0, [r1]
assembles as this:
$ arm-none-eabi-as -o ldr.o ldr.s
$ arm-none-eabi-objdump -d ldr.o
ldr.o: file format elf32-littlearm
Disassembly of section .text:
00000000 <.text>:
0: e59f0000 ldr r0, [pc] ; 8 <.text+0x8>
4: e59f0000 ldr r0, [pc] ; c <.text+0xc>
8: e5910000 ldr r0, [r1]
c: e5910000 ldr r0, [r1]
i.e. there is absolutely no difference whatever between the two
instruction forms.
Furthermore the omission of the insignificant zero offset is explicitly
permitted by the architecture manual with the following note found on the
page defining this particular addressing mode being used:
"5.2.2 Load and Store Word or Unsigned Byte -- Immediate offset
[...]
Offset of zero The syntax [<Rn>] is treated as an abbreviation for
[<Rn>, #0], unless the instruction is one that only allows
post-indexed addressing modes (LDRBT, LDRT, STRBT or
STRT)."
and given the disassembly is typically meant to be examined by a human
being, omitting redundant information is usually good for readability.
Maciej