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[Committed] S/390: Register pair checking for floating point
- From: "Andreas Krebbel" <krebbel at linux dot vnet dot ibm dot com>
- To: binutils at sourceware dot org
- Date: Tue, 24 May 2011 18:15:28 +0200
- Subject: [Committed] S/390: Register pair checking for floating point
- References: <20110524134218.GA6015@bart>
Hi,
the attached patch fixes the register pair operand check for floating
point registers. Unfortunately I had to adjust several testsuite
instructions again what makes the bulk of the patch.
Applied to mainline.
Bye,
-Andreas-
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config/tc-s390.c (md_gather_operands): Fix check for floating
register pair operands.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* opcode/s390.h: Replace S390_OPERAND_REG_EVEN with
S390_OPERAND_REG_PAIR.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.c: Replace S390_OPERAND_REG_EVEN with
S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
* s390-opc.txt: Fix cxr instruction type.
2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gas/s390/esa-g5.d: Fix fp register pair operands.
* gas/s390/esa-g5.s: Likewise.
* gas/s390/zarch-z196.d: Likewise.
* gas/s390/zarch-z196.s: Likewise.
* gas/s390/zarch-z9-109.d: Likewise.
* gas/s390/zarch-z9-109.s: Likewise.
* gas/s390/zarch-z9-ec.d: Likewise.
* gas/s390/zarch-z9-ec.s: Likewise.
Index: gas/config/tc-s390.c
===================================================================
--- gas/config/tc-s390.c.orig
+++ gas/config/tc-s390.c
@@ -1267,9 +1267,20 @@ md_gather_operands (char *str,
&& ex.X_add_number == 0
&& warn_areg_zero)
as_warn (_("base register specified but zero"));
- if ((operand->flags & S390_OPERAND_REG_EVEN)
+ if ((operand->flags & S390_OPERAND_GPR)
+ && (operand->flags & S390_OPERAND_REG_PAIR)
&& (ex.X_add_number & 1))
- as_fatal (_("odd numbered register specified as register pair"));
+ as_fatal (_("odd numbered general purpose register specified as "
+ "register pair"));
+ if ((operand->flags & S390_OPERAND_FPR)
+ && (operand->flags & S390_OPERAND_REG_PAIR)
+ && ex.X_add_number != 0 && ex.X_add_number != 1
+ && ex.X_add_number != 4 && ex.X_add_number != 5
+ && ex.X_add_number != 8 && ex.X_add_number != 9
+ && ex.X_add_number != 12 && ex.X_add_number != 13)
+ as_fatal (_("invalid floating point register pair. Valid fp "
+ "register pair operands are 0, 1, 4, 5, 8, 9, "
+ "12 or 13."));
s390_insert_operand (insn, operand, ex.X_add_number, NULL, 0);
}
}
Index: include/opcode/s390.h
===================================================================
--- include/opcode/s390.h.orig
+++ include/opcode/s390.h
@@ -147,7 +147,7 @@ extern const struct s390_operand s390_op
the instruction may be optional. */
#define S390_OPERAND_OPTIONAL 0x400
-/* The operand needs to be an even register number. */
-#define S390_OPERAND_REG_EVEN 0x800
+/* The operand needs to be a valid GP or FP register pair. */
+#define S390_OPERAND_REG_PAIR 0x800
#endif /* S390_H */
Index: opcodes/s390-opc.c
===================================================================
--- opcodes/s390-opc.c.orig
+++ opcodes/s390-opc.c
@@ -67,19 +67,19 @@ const struct s390_operand s390_operands[
/* General purpose register pair operands. */
#define RE_8 10 /* GPR starting at position 8 */
- { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+ { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
#define RE_12 11 /* GPR starting at position 12 */
- { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+ { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
#define RE_16 12 /* GPR starting at position 16 */
- { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+ { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
#define RE_20 13 /* GPR starting at position 20 */
- { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+ { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
#define RE_24 14 /* GPR starting at position 24 */
- { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+ { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
#define RE_28 15 /* GPR starting at position 28 */
- { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+ { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
#define RE_32 16 /* GPR starting at position 32 */
- { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN },
+ { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR },
/* Floating point register operands. */
@@ -102,19 +102,19 @@ const struct s390_operand s390_operands[
/* Floating point register pair operands. */
#define FE_8 24 /* FPR starting at position 8 */
- { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+ { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
#define FE_12 25 /* FPR starting at position 12 */
- { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+ { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
#define FE_16 26 /* FPR starting at position 16 */
- { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+ { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
#define FE_20 27 /* FPR starting at position 16 */
- { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+ { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
#define FE_24 28 /* FPR starting at position 24 */
- { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+ { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
#define FE_28 29 /* FPR starting at position 28 */
- { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+ { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
#define FE_32 30 /* FPR starting at position 32 */
- { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN },
+ { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR },
/* Access register operands. */
@@ -336,7 +336,7 @@ const struct s390_operand s390_operands[
#define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */
#define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */
#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */
-#define INSTR_RRF_0UFEF 4, { F_24,FE_28,U4_20,0,0,0 } /* e.g. lxdtr */
+#define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */
#define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */
#define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */
#define INSTR_RRF_M0RR 4, { R_24,R_28,M_16OPT,0,0,0 } /* e.g. sske */
Index: gas/testsuite/gas/s390/esa-g5.d
===================================================================
--- gas/testsuite/gas/s390/esa-g5.d.orig
+++ gas/testsuite/gas/s390/esa-g5.d
@@ -25,8 +25,8 @@ Disassembly of section .text:
.*: 3e 69 [ ]*aur %f6,%f9
.*: 6e 65 af ff [ ]*aw %f6,4095\(%r5,%r10\)
.*: 2e 69 [ ]*awr %f6,%f9
-.*: b3 4a 00 68 [ ]*axbr %f6,%f8
-.*: 36 68 [ ]*axr %f6,%f8
+.*: b3 4a 00 48 [ ]*axbr %f4,%f8
+.*: 36 48 [ ]*axr %f4,%f8
.*: 47 f5 af ff [ ]*b 4095\(%r5,%r10\)
.*: b2 40 00 69 [ ]*bakr %r6,%r9
.*: 45 65 af ff [ ]*bal %r6,4095\(%r5,%r10\)
@@ -109,7 +109,7 @@ Disassembly of section .text:
.*: b3 9a 50 58 [ ]*cfxbr %r5,5,%f8
.*: b3 b9 90 65 [ ]*cfdr %r6,9,%f5
.*: b3 b8 90 65 [ ]*cfer %r6,9,%f5
-.*: b3 ba 90 56 [ ]*cfxr %r5,9,%f6
+.*: b3 ba 90 54 [ ]*cfxr %r5,9,%f4
.*: 49 65 af ff [ ]*ch %r6,4095\(%r5,%r10\)
.*: a7 6e 80 01 [ ]*chi %r6,-32767
.*: b2 41 00 69 [ ]*cksm %r6,%r9
@@ -133,10 +133,10 @@ Disassembly of section .text:
.*: b2 a6 00 68 [ ]*cuutf %r6,%r8
.*: 4f 65 af ff [ ]*cvb %r6,4095\(%r5,%r10\)
.*: 4e 65 af ff [ ]*cvd %r6,4095\(%r5,%r10\)
-.*: b3 49 00 68 [ ]*cxbr %f6,%f8
-.*: b3 96 00 69 [ ]*cxfbr %f6,%r9
-.*: b3 b6 00 69 [ ]*cxfr %f6,%r9
-.*: b3 69 00 69 [ ]*cxr %f6,%f9
+.*: b3 49 00 58 [ ]*cxbr %f5,%f8
+.*: b3 96 00 59 [ ]*cxfbr %f5,%r9
+.*: b3 b6 00 59 [ ]*cxfr %f5,%r9
+.*: b3 69 00 59 [ ]*cxr %f5,%f9
.*: 5d 65 af ff [ ]*d %r6,4095\(%r5,%r10\)
.*: 6d 65 af ff [ ]*dd %f6,4095\(%r5,%r10\)
.*: ed 65 af ff 00 1d [ ]*ddb %f6,4095\(%r5,%r10\)
@@ -151,8 +151,8 @@ Disassembly of section .text:
.*: b3 53 9a 65 [ ]*diebr %f6,%f9,%f5,10
.*: fd 58 5f ff af ff [ ]*dp 4095\(6,%r5\),4095\(9,%r10\)
.*: 1d 69 [ ]*dr %r6,%r9
-.*: b3 4d 00 68 [ ]*dxbr %f6,%f8
-.*: b2 2d 00 68 [ ]*dxr %f6,%f8
+.*: b3 4d 00 58 [ ]*dxbr %f5,%f8
+.*: b2 2d 00 58 [ ]*dxr %f5,%f8
.*: b2 4f 00 69 [ ]*ear %r6,%a9
.*: de ff 5f ff af ff [ ]*ed 4095\(256,%r5\),4095\(%r10\)
.*: df ff 5f ff af ff [ ]*edmk 4095\(256,%r5\),4095\(%r10\)
@@ -166,8 +166,8 @@ Disassembly of section .text:
.*: b3 7f 00 69 [ ]*fidr %f6,%f9
.*: b3 57 50 69 [ ]*fiebr %f6,5,%f9
.*: b3 77 00 69 [ ]*fier %f6,%f9
-.*: b3 47 50 68 [ ]*fixbr %f6,5,%f8
-.*: b3 67 00 68 [ ]*fixr %f6,%f8
+.*: b3 47 50 58 [ ]*fixbr %f5,5,%f8
+.*: b3 67 00 58 [ ]*fixr %f5,%f8
.*: 24 69 [ ]*hdr %f6,%f9
.*: 34 69 [ ]*her %f6,%f9
.*: b2 31 00 00 [ ]*hsch
@@ -216,21 +216,21 @@ Disassembly of section .text:
.*: 33 69 [ ]*lcer %f6,%f9
.*: 13 69 [ ]*lcr %r6,%r9
.*: b7 69 5f ff [ ]*lctl %c6,%c9,4095\(%r5\)
-.*: b3 43 00 68 [ ]*lcxbr %f6,%f8
-.*: b3 63 00 68 [ ]*lcxr %f6,%f8
+.*: b3 43 00 58 [ ]*lcxbr %f5,%f8
+.*: b3 63 00 58 [ ]*lcxr %f5,%f8
.*: 68 65 af ff [ ]*ld %f6,4095\(%r5,%r10\)
.*: ed 65 af ff 00 24 [ ]*lde %f6,4095\(%r5,%r10\)
.*: ed 65 af ff 00 04 [ ]*ldeb %f6,4095\(%r5,%r10\)
.*: b3 04 00 69 [ ]*ldebr %f6,%f9
.*: b3 24 00 69 [ ]*lder %f6,%f9
.*: 28 69 [ ]*ldr %f6,%f9
-.*: b3 45 00 68 [ ]*ldxbr %f6,%f8
+.*: b3 45 00 58 [ ]*ldxbr %f5,%f8
.*: 25 68 [ ]*ldxr %f6,%f8
.*: 78 65 af ff [ ]*le %f6,4095\(%r5,%r10\)
.*: b3 44 00 69 [ ]*ledbr %f6,%f9
.*: 35 69 [ ]*ledr %f6,%f9
.*: 38 69 [ ]*ler %f6,%f9
-.*: b3 46 00 68 [ ]*lexbr %f6,%f8
+.*: b3 46 00 58 [ ]*lexbr %f5,%f8
.*: b3 66 00 68 [ ]*lexr %f6,%f8
.*: b2 9d 5f ff [ ]*lfpc 4095\(%r5\)
.*: 48 65 af ff [ ]*lh %r6,4095\(%r5,%r10\)
@@ -241,16 +241,16 @@ Disassembly of section .text:
.*: b3 01 00 69 [ ]*lnebr %f6,%f9
.*: 31 69 [ ]*lner %f6,%f9
.*: 11 69 [ ]*lnr %r6,%r9
-.*: b3 41 00 68 [ ]*lnxbr %f6,%f8
-.*: b3 61 00 68 [ ]*lnxr %f6,%f8
+.*: b3 41 00 58 [ ]*lnxbr %f5,%f8
+.*: b3 61 00 58 [ ]*lnxr %f5,%f8
.*: b3 10 00 69 [ ]*lpdbr %f6,%f9
.*: 20 69 [ ]*lpdr %f6,%f9
.*: b3 00 00 69 [ ]*lpebr %f6,%f9
.*: 30 69 [ ]*lper %f6,%f9
.*: 10 69 [ ]*lpr %r6,%r9
.*: 82 00 5f ff [ ]*lpsw 4095\(%r5\)
-.*: b3 40 00 68 [ ]*lpxbr %f6,%f8
-.*: b3 60 00 68 [ ]*lpxr %f6,%f8
+.*: b3 40 00 58 [ ]*lpxbr %f5,%f8
+.*: b3 60 00 58 [ ]*lpxr %f5,%f8
.*: 18 69 [ ]*lr %r6,%r9
.*: b1 65 af ff [ ]*lra %r6,4095\(%r5,%r10\)
.*: 25 78 [ ]*ldxr %f7,%f8
@@ -260,21 +260,21 @@ Disassembly of section .text:
.*: b3 02 00 69 [ ]*ltebr %f6,%f9
.*: 32 69 [ ]*lter %f6,%f9
.*: 12 69 [ ]*ltr %r6,%r9
-.*: b3 42 00 68 [ ]*ltxbr %f6,%f8
-.*: b3 62 00 68 [ ]*ltxr %f6,%f8
+.*: b3 42 00 58 [ ]*ltxbr %f5,%f8
+.*: b3 62 00 58 [ ]*ltxr %f5,%f8
.*: b2 4b 00 69 [ ]*lura %r6,%r9
-.*: ed 65 af ff 00 25 [ ]*lxd %f6,4095\(%r5,%r10\)
-.*: ed 65 af ff 00 05 [ ]*lxdb %f6,4095\(%r5,%r10\)
-.*: b3 05 00 69 [ ]*lxdbr %f6,%f9
-.*: b3 25 00 69 [ ]*lxdr %f6,%f9
-.*: ed 65 af ff 00 26 [ ]*lxe %f6,4095\(%r5,%r10\)
-.*: ed 65 af ff 00 06 [ ]*lxeb %f6,4095\(%r5,%r10\)
-.*: b3 06 00 69 [ ]*lxebr %f6,%f9
-.*: b3 26 00 69 [ ]*lxer %f6,%f9
-.*: b3 65 00 68 [ ]*lxr %f6,%f8
+.*: ed 55 af ff 00 25 [ ]*lxd %f5,4095\(%r5,%r10\)
+.*: ed 55 af ff 00 05 [ ]*lxdb %f5,4095\(%r5,%r10\)
+.*: b3 05 00 59 [ ]*lxdbr %f5,%f9
+.*: b3 25 00 59 [ ]*lxdr %f5,%f9
+.*: ed 55 af ff 00 26 [ ]*lxe %f5,4095\(%r5,%r10\)
+.*: ed 55 af ff 00 06 [ ]*lxeb %f5,4095\(%r5,%r10\)
+.*: b3 06 00 59 [ ]*lxebr %f5,%f9
+.*: b3 26 00 59 [ ]*lxer %f5,%f9
+.*: b3 65 00 58 [ ]*lxr %f5,%f8
.*: b3 75 00 60 [ ]*lzdr %f6
.*: b3 74 00 60 [ ]*lzer %f6
-.*: b3 76 00 60 [ ]*lzxr %f6
+.*: b3 76 00 50 [ ]*lzxr %f5
.*: 5c 65 af ff [ ]*m %r6,4095\(%r5,%r10\)
.*: ed 95 af ff 60 1e [ ]*madb %f6,%f9,4095\(%r5,%r10\)
.*: b3 1e 60 95 [ ]*madbr %f6,%f9,%f5
@@ -323,12 +323,12 @@ Disassembly of section .text:
.*: b2 54 00 69 [ ]*mvpg %r6,%r9
.*: b2 55 00 69 [ ]*mvst %r6,%r9
.*: d3 ff 5f ff af ff [ ]*mvz 4095\(256,%r5\),4095\(%r10\)
-.*: b3 4c 00 68 [ ]*mxbr %f6,%f8
-.*: 67 65 af ff [ ]*mxd %f6,4095\(%r5,%r10\)
-.*: ed 65 af ff 00 07 [ ]*mxdb %f6,4095\(%r5,%r10\)
-.*: b3 07 00 69 [ ]*mxdbr %f6,%f9
-.*: 27 69 [ ]*mxdr %f6,%f9
-.*: 26 68 [ ]*mxr %f6,%f8
+.*: b3 4c 00 58 [ ]*mxbr %f5,%f8
+.*: 67 55 af ff [ ]*mxd %f5,4095\(%r5,%r10\)
+.*: ed 55 af ff 00 07 [ ]*mxdb %f5,4095\(%r5,%r10\)
+.*: b3 07 00 59 [ ]*mxdbr %f5,%f9
+.*: 27 59 [ ]*mxdr %f5,%f9
+.*: 26 58 [ ]*mxr %f5,%f8
.*: 54 65 af ff [ ]*n %r6,4095\(%r5,%r10\)
.*: d4 ff 5f ff af ff [ ]*nc 4095\(256,%r5\),4095\(%r10\)
.*: 94 ff 5f ff [ ]*ni 4095\(%r5\),255
@@ -395,8 +395,8 @@ Disassembly of section .text:
.*: ed 65 af ff 00 14 [ ]*sqeb %f6,4095\(%r5,%r10\)
.*: b3 14 00 69 [ ]*sqebr %f6,%f9
.*: b2 45 00 69 [ ]*sqer %f6,%f9
-.*: b3 16 00 68 [ ]*sqxbr %f6,%f8
-.*: b3 36 00 68 [ ]*sqxr %f6,%f8
+.*: b3 16 00 58 [ ]*sqxbr %f5,%f8
+.*: b3 36 00 58 [ ]*sqxr %f5,%f8
.*: 1b 69 [ ]*sr %r6,%r9
.*: 8a 60 5f ff [ ]*sra %r6,4095\(%r5\)
.*: 8e 60 5f ff [ ]*srda %r6,4095\(%r5\)
@@ -438,15 +438,15 @@ Disassembly of section .text:
.*: 0a ff [ ]*svc 255
.*: 6f 65 af ff [ ]*sw %f6,4095\(%r5,%r10\)
.*: 2f 69 [ ]*swr %f6,%f9
-.*: b3 4b 00 68 [ ]*sxbr %f6,%f8
-.*: 37 68 [ ]*sxr %f6,%f8
+.*: b3 4b 00 58 [ ]*sxbr %f5,%f8
+.*: 37 58 [ ]*sxr %f5,%f8
.*: b2 4c 00 69 [ ]*tar %a6,%r9
.*: b2 2c 00 06 [ ]*tb %r6
.*: b3 51 50 69 [ ]*tbdr %f6,5,%f9
.*: b3 50 50 69 [ ]*tbedr %f6,5,%f9
.*: ed 65 af ff 00 11 [ ]*tcdb %f6,4095\(%r5,%r10\)
.*: ed 65 af ff 00 10 [ ]*tceb %f6,4095\(%r5,%r10\)
-.*: ed 65 af ff 00 12 [ ]*tcxb %f6,4095\(%r5,%r10\)
+.*: ed 55 af ff 00 12 [ ]*tcxb %f5,4095\(%r5,%r10\)
.*: b3 58 00 69 [ ]*thder %f6,%f9
.*: b3 59 00 69 [ ]*thdr %f6,%f9
.*: 91 ff 5f ff [ ]*tm 4095\(%r5\),255
Index: gas/testsuite/gas/s390/esa-g5.s
===================================================================
--- gas/testsuite/gas/s390/esa-g5.s.orig
+++ gas/testsuite/gas/s390/esa-g5.s
@@ -19,8 +19,8 @@ foo:
aur %f6,%f9
aw %f6,4095(%r5,%r10)
awr %f6,%f9
- axbr %f6,%f8
- axr %f6,%f8
+ axbr %f4,%f8
+ axr %f4,%f8
b 4095(%r5,%r10)
bakr %r6,%r9
bal %r6,4095(%r5,%r10)
@@ -103,7 +103,7 @@ foo:
cfxbr %r5,5,%f8
cfdr %r6,9,%f5
cfer %r6,9,%f5
- cfxr %r5,9,%f6
+ cfxr %r5,9,%f4
ch %r6,4095(%r5,%r10)
chi %r6,-32767
cksm %r6,%r9
@@ -127,10 +127,10 @@ foo:
cuutf %r6,%r8
cvb %r6,4095(%r5,%r10)
cvd %r6,4095(%r5,%r10)
- cxbr %f6,%f8
- cxfbr %f6,%r9
- cxfr %f6,%r9
- cxr %f6,%f9
+ cxbr %f5,%f8
+ cxfbr %f5,%r9
+ cxfr %f5,%r9
+ cxr %f5,%f9
d %r6,4095(%r5,%r10)
dd %f6,4095(%r5,%r10)
ddb %f6,4095(%r5,%r10)
@@ -145,8 +145,8 @@ foo:
diebr %f6,%r9,%r5,10
dp 4095(6,%r5),4095(9,%r10)
dr %r6,%r9
- dxbr %f6,%f8
- dxr %f6,%f8
+ dxbr %f5,%f8
+ dxr %f5,%f8
ear %r6,%a9
ed 4095(256,%r5),4095(%r10)
edmk 4095(256,%r5),4095(%r10)
@@ -160,8 +160,8 @@ foo:
fidr %f6,%f9
fiebr %f6,5,%f9
fier %f6,%f9
- fixbr %f6,5,%f8
- fixr %f6,%f8
+ fixbr %f5,5,%f8
+ fixr %f5,%f8
hdr %f6,%f9
her %f6,%f9
hsch
@@ -210,21 +210,21 @@ foo:
lcer %f6,%f9
lcr %r6,%r9
lctl %c6,%c9,4095(%r5)
- lcxbr %f6,%f8
- lcxr %f6,%f8
+ lcxbr %f5,%f8
+ lcxr %f5,%f8
ld %f6,4095(%r5,%r10)
lde %f6,4095(%r5,%r10)
ldeb %f6,4095(%r5,%r10)
ldebr %f6,%f9
lder %f6,%f9
ldr %f6,%f9
- ldxbr %f6,%f8
+ ldxbr %f5,%f8
ldxr %f6,%f8
le %f6,4095(%r5,%r10)
ledbr %f6,%f9
ledr %f6,%f9
ler %f6,%f9
- lexbr %f6,%f8
+ lexbr %f5,%f8
lexr %f6,%f8
lfpc 4095(%r5)
lh %r6,4095(%r5,%r10)
@@ -235,16 +235,16 @@ foo:
lnebr %f6,%f9
lner %f6,%f9
lnr %r6,%r9
- lnxbr %f6,%f8
- lnxr %f6,%f8
+ lnxbr %f5,%f8
+ lnxr %f5,%f8
lpdbr %f6,%f9
lpdr %f6,%f9
lpebr %f6,%f9
lper %f6,%f9
lpr %r6,%r9
lpsw 4095(%r5)
- lpxbr %f6,%f8
- lpxr %f6,%f8
+ lpxbr %f5,%f8
+ lpxr %f5,%f8
lr %r6,%r9
lra %r6,4095(%r5,%r10)
lrdr %f7,%f8
@@ -254,21 +254,21 @@ foo:
ltebr %f6,%f9
lter %f6,%f9
ltr %r6,%r9
- ltxbr %f6,%f8
- ltxr %f6,%f8
+ ltxbr %f5,%f8
+ ltxr %f5,%f8
lura %r6,%r9
- lxd %f6,4095(%r5,%r10)
- lxdb %f6,4095(%r5,%r10)
- lxdbr %f6,%f9
- lxdr %f6,%f9
- lxe %f6,4095(%r5,%r10)
- lxeb %f6,4095(%r5,%r10)
- lxebr %f6,%f9
- lxer %f6,%f9
- lxr %f6,%f8
+ lxd %f5,4095(%r5,%r10)
+ lxdb %f5,4095(%r5,%r10)
+ lxdbr %f5,%f9
+ lxdr %f5,%f9
+ lxe %f5,4095(%r5,%r10)
+ lxeb %f5,4095(%r5,%r10)
+ lxebr %f5,%f9
+ lxer %f5,%f9
+ lxr %f5,%f8
lzdr %f6
lzer %f6
- lzxr %f6
+ lzxr %f5
m %r6,4095(%r5,%r10)
madb %f6,%f9,4095(%r5,%r10)
madbr %f6,%f9,%f5
@@ -317,12 +317,12 @@ foo:
mvpg %r6,%r9
mvst %r6,%r9
mvz 4095(256,%r5),4095(%r10)
- mxbr %f6,%f8
- mxd %f6,4095(%r5,%r10)
- mxdb %f6,4095(%r5,%r10)
- mxdbr %f6,%f9
- mxdr %f6,%f9
- mxr %f6,%f8
+ mxbr %f5,%f8
+ mxd %f5,4095(%r5,%r10)
+ mxdb %f5,4095(%r5,%r10)
+ mxdbr %f5,%f9
+ mxdr %f5,%f9
+ mxr %f5,%f8
n %r6,4095(%r5,%r10)
nc 4095(256,%r5),4095(%r10)
ni 4095(%r5),255
@@ -389,8 +389,8 @@ foo:
sqeb %f6,4095(%r5,%r10)
sqebr %f6,%f9
sqer %f6,%f9
- sqxbr %f6,%f8
- sqxr %f6,%f8
+ sqxbr %f5,%f8
+ sqxr %f5,%f8
sr %r6,%r9
sra %r6,4095(%r5)
srda %r6,4095(%r5)
@@ -432,15 +432,15 @@ foo:
svc 255
sw %f6,4095(%r5,%r10)
swr %f6,%f9
- sxbr %f6,%f8
- sxr %f6,%f8
+ sxbr %f5,%f8
+ sxr %f5,%f8
tar %a6,%r9
tb %r6
tbdr %r6,5,%r9
tbedr %r6,5,%r9
tcdb %f6,4095(%r5,%r10)
tceb %f6,4095(%r5,%r10)
- tcxb %f6,4095(%r5,%r10)
+ tcxb %f5,4095(%r5,%r10)
thder %f6,%f9
thdr %f6,%f9
tm 4095(%r5),255
Index: gas/testsuite/gas/s390/zarch-z196.d
===================================================================
--- gas/testsuite/gas/s390/zarch-z196.d.orig
+++ gas/testsuite/gas/s390/zarch-z196.d
@@ -200,16 +200,16 @@ Disassembly of section .text:
.*: b9 ae 00 67 [ ]*rrbm %r6,%r7
.*: b3 94 37 59 [ ]*cefbra %f5,3,%r9,7
.*: b3 95 37 59 [ ]*cdfbra %f5,3,%r9,7
-.*: b3 96 37 69 [ ]*cxfbra %f6,3,%r9,7
+.*: b3 96 37 59 [ ]*cxfbra %f5,3,%r9,7
.*: b3 a4 37 59 [ ]*cegbra %f5,3,%r9,7
.*: b3 a5 37 59 [ ]*cdgbra %f5,3,%r9,7
-.*: b3 a6 37 69 [ ]*cxgbra %f6,3,%r9,7
+.*: b3 a6 37 59 [ ]*cxgbra %f5,3,%r9,7
.*: b3 90 37 59 [ ]*celfbr %f5,3,%r9,7
.*: b3 91 37 59 [ ]*cdlfbr %f5,3,%r9,7
-.*: b3 92 37 69 [ ]*cxlfbr %f6,3,%r9,7
+.*: b3 92 37 59 [ ]*cxlfbr %f5,3,%r9,7
.*: b3 a0 37 59 [ ]*celgbr %f5,3,%r9,7
.*: b3 a1 37 59 [ ]*cdlgbr %f5,3,%r9,7
-.*: b3 a2 37 69 [ ]*cxlgbr %f6,3,%r9,7
+.*: b3 a2 37 59 [ ]*cxlgbr %f5,3,%r9,7
.*: b3 98 37 59 [ ]*cfebra %r5,3,%f9,7
.*: b3 99 37 59 [ ]*cfdbra %r5,3,%f9,7
.*: b3 9a 37 58 [ ]*cfxbra %r5,3,%f8,7
@@ -224,18 +224,18 @@ Disassembly of section .text:
.*: b3 ae 37 58 [ ]*clgxbr %r5,3,%f8,7
.*: b3 57 37 59 [ ]*fiebra %f5,3,%f9,7
.*: b3 5f 37 59 [ ]*fidbra %f5,3,%f9,7
-.*: b3 47 37 68 [ ]*fixbra %f6,3,%f8,7
+.*: b3 47 37 58 [ ]*fixbra %f5,3,%f8,7
.*: b3 44 37 59 [ ]*ledbra %f5,3,%f9,7
-.*: b3 45 37 68 [ ]*ldxbra %f6,3,%f8,7
-.*: b3 46 37 68 [ ]*lexbra %f6,3,%f8,7
+.*: b3 45 37 58 [ ]*ldxbra %f5,3,%f8,7
+.*: b3 46 37 58 [ ]*lexbra %f5,3,%f8,7
.*: b3 d2 97 35 [ ]*adtra %f3,%f5,%f9,7
-.*: b3 da 67 24 [ ]*axtra %f2,%f4,%f6,7
+.*: b3 da 57 14 [ ]*axtra %f1,%f4,%f5,7
.*: b3 f1 37 59 [ ]*cdgtra %f5,3,%r9,7
.*: b9 51 37 59 [ ]*cdftr %f5,3,%r9,7
-.*: b9 59 37 69 [ ]*cxftr %f6,3,%r9,7
-.*: b3 f9 37 69 [ ]*cxgtra %f6,3,%r9,7
+.*: b9 59 37 59 [ ]*cxftr %f5,3,%r9,7
+.*: b3 f9 37 59 [ ]*cxgtra %f5,3,%r9,7
.*: b9 52 37 59 [ ]*cdlgtr %f5,3,%r9,7
-.*: b9 5a 37 69 [ ]*cxlgtr %f6,3,%r9,7
+.*: b9 5a 37 59 [ ]*cxlgtr %f5,3,%r9,7
.*: b9 53 37 59 [ ]*cdlftr %f5,3,%r9,7
.*: b9 5b 37 59 [ ]*cxlftr %f5,3,%r9,7
.*: b3 e1 37 59 [ ]*cgdtra %r5,3,%f9,7
@@ -247,9 +247,9 @@ Disassembly of section .text:
.*: b9 43 37 59 [ ]*clfdtr %r5,3,%f9,7
.*: b9 4b 37 58 [ ]*clfxtr %r5,3,%f8,7
.*: b3 d1 97 35 [ ]*ddtra %f3,%f5,%f9,7
-.*: b3 d9 67 24 [ ]*dxtra %f2,%f4,%f6,7
+.*: b3 d9 57 14 [ ]*dxtra %f1,%f4,%f5,7
.*: b3 d0 97 35 [ ]*mdtra %f3,%f5,%f9,7
-.*: b3 d8 67 24 [ ]*mxtra %f2,%f4,%f6,7
+.*: b3 d8 57 14 [ ]*mxtra %f1,%f4,%f5,7
.*: b3 d3 97 35 [ ]*sdtra %f3,%f5,%f9,7
-.*: b3 db 67 24 [ ]*sxtra %f2,%f4,%f6,7
+.*: b3 db 57 14 [ ]*sxtra %f1,%f4,%f5,7
.*: b2 b8 7f a0 [ ]*srnmb 4000\(%r7\)
Index: gas/testsuite/gas/s390/zarch-z196.s
===================================================================
--- gas/testsuite/gas/s390/zarch-z196.s.orig
+++ gas/testsuite/gas/s390/zarch-z196.s
@@ -202,16 +202,16 @@ foo:
cefbra %f5,3,%r9,7
cdfbra %f5,3,%r9,7
- cxfbra %f6,3,%r9,7
+ cxfbra %f5,3,%r9,7
cegbra %f5,3,%r9,7
cdgbra %f5,3,%r9,7
- cxgbra %f6,3,%r9,7
+ cxgbra %f5,3,%r9,7
celfbr %f5,3,%r9,7
cdlfbr %f5,3,%r9,7
- cxlfbr %f6,3,%r9,7
+ cxlfbr %f5,3,%r9,7
celgbr %f5,3,%r9,7
cdlgbr %f5,3,%r9,7
- cxlgbr %f6,3,%r9,7
+ cxlgbr %f5,3,%r9,7
cfebra %r5,3,%f9,7
cfdbra %r5,3,%f9,7
cfxbra %r5,3,%f8,7
@@ -226,18 +226,18 @@ foo:
clgxbr %r5,3,%f8,7
fiebra %f5,3,%f9,7
fidbra %f5,3,%f9,7
- fixbra %f6,3,%f8,7
+ fixbra %f5,3,%f8,7
ledbra %f5,3,%f9,7
- ldxbra %f6,3,%f8,7
- lexbra %f6,3,%f8,7
+ ldxbra %f5,3,%f8,7
+ lexbra %f5,3,%f8,7
adtra %f3,%f5,%f9,7
- axtra %f2,%f4,%f6,7
+ axtra %f1,%f4,%f5,7
cdgtra %f5,3,%r9,7
cdftr %f5,3,%r9,7
- cxftr %f6,3,%r9,7
- cxgtra %f6,3,%r9,7
+ cxftr %f5,3,%r9,7
+ cxgtra %f5,3,%r9,7
cdlgtr %f5,3,%r9,7
- cxlgtr %f6,3,%r9,7
+ cxlgtr %f5,3,%r9,7
cdlftr %f5,3,%r9,7
cxlftr %f5,3,%r9,7
cgdtra %r5,3,%f9,7
@@ -249,9 +249,9 @@ foo:
clfdtr %r5,3,%f9,7
clfxtr %r5,3,%f8,7
ddtra %f3,%f5,%f9,7
- dxtra %f2,%f4,%f6,7
+ dxtra %f1,%f4,%f5,7
mdtra %f3,%f5,%f9,7
- mxtra %f2,%f4,%f6,7
+ mxtra %f1,%f4,%f5,7
sdtra %f3,%f5,%f9,7
- sxtra %f2,%f4,%f6,7
+ sxtra %f1,%f4,%f5,7
srnmb 4000(%r7)
Index: gas/testsuite/gas/s390/zarch-z9-109.d
===================================================================
--- gas/testsuite/gas/s390/zarch-z9-109.d.orig
+++ gas/testsuite/gas/s390/zarch-z9-109.d
@@ -54,7 +54,7 @@ Disassembly of section .text:
.*: b3 3b 60 95 [ ]*myr %f6,%f9,%f5
.*: b3 3d 60 95 [ ]*myhr %f6,%f9,%f5
.*: b3 39 60 95 [ ]*mylr %f6,%f9,%f5
-.*: ed 95 af ff 60 3b [ ]*my %f6,%f9,4095\(%r5,%r10\)
+.*: ed 95 af ff 50 3b [ ]*my %f5,%f9,4095\(%r5,%r10\)
.*: ed 95 af ff 60 3d [ ]*myh %f6,%f9,4095\(%r5,%r10\)
.*: ed 95 af ff 60 39 [ ]*myl %f6,%f9,4095\(%r5,%r10\)
.*: b3 3a 60 95 [ ]*mayr %f6,%f9,%f5
Index: gas/testsuite/gas/s390/zarch-z9-109.s
===================================================================
--- gas/testsuite/gas/s390/zarch-z9-109.s.orig
+++ gas/testsuite/gas/s390/zarch-z9-109.s
@@ -48,7 +48,7 @@ foo:
myr %f6,%f9,%f5
myhr %f6,%f9,%f5
mylr %f6,%f9,%f5
- my %f6,%f9,4095(%r5,%r10)
+ my %f5,%f9,4095(%r5,%r10)
myh %f6,%f9,4095(%r5,%r10)
myl %f6,%f9,4095(%r5,%r10)
mayr %f6,%f9,%f5
Index: gas/testsuite/gas/s390/zarch-z9-ec.d
===================================================================
--- gas/testsuite/gas/s390/zarch-z9-ec.d.orig
+++ gas/testsuite/gas/s390/zarch-z9-ec.d
@@ -13,62 +13,62 @@ Disassembly of section .text:
.*: b3 c1 00 62 [ ]*ldgr %f6,%r2
.*: b3 cd 00 26 [ ]*lgdr %r2,%f6
.*: b3 d2 40 62 [ ]*adtr %f6,%f2,%f4
-.*: b3 da 40 62 [ ]*axtr %f6,%f2,%f4
+.*: b3 da 40 89 [ ]*axtr %f8,%f9,%f4
.*: b3 e4 00 62 [ ]*cdtr %f6,%f2
-.*: b3 ec 00 62 [ ]*cxtr %f6,%f2
+.*: b3 ec 00 10 [ ]*cxtr %f1,%f0
.*: b3 e0 00 62 [ ]*kdtr %f6,%f2
.*: b3 e8 00 62 [ ]*kxtr %f6,%f2
.*: b3 f4 00 62 [ ]*cedtr %f6,%f2
-.*: b3 fc 00 62 [ ]*cextr %f6,%f2
+.*: b3 fc 00 10 [ ]*cextr %f1,%f0
.*: b3 f1 00 62 [ ]*cdgtr %f6,%r2
-.*: b3 f9 00 62 [ ]*cxgtr %f6,%r2
+.*: b3 f9 00 12 [ ]*cxgtr %f1,%r2
.*: b3 f3 00 62 [ ]*cdstr %f6,%r2
.*: b3 fb 00 62 [ ]*cxstr %f6,%r2
.*: b3 f2 00 62 [ ]*cdutr %f6,%r2
-.*: b3 fa 00 62 [ ]*cxutr %f6,%r2
+.*: b3 fa 00 12 [ ]*cxutr %f1,%r2
.*: b3 e1 10 26 [ ]*cgdtr %r2,1,%f6
-.*: b3 e9 10 26 [ ]*cgxtr %r2,1,%f6
+.*: b3 e9 10 21 [ ]*cgxtr %r2,1,%f1
.*: b3 e3 00 26 [ ]*csdtr %r2,%f6
-.*: b3 eb 00 26 [ ]*csxtr %r2,%f6
+.*: b3 eb 00 21 [ ]*csxtr %r2,%f1
.*: b3 e2 00 26 [ ]*cudtr %r2,%f6
-.*: b3 ea 00 26 [ ]*cuxtr %r2,%f6
+.*: b3 ea 00 21 [ ]*cuxtr %r2,%f1
.*: b3 d1 40 62 [ ]*ddtr %f6,%f2,%f4
-.*: b3 d9 40 62 [ ]*dxtr %f6,%f2,%f4
+.*: b3 d9 40 10 [ ]*dxtr %f1,%f0,%f4
.*: b3 e5 00 26 [ ]*eedtr %r2,%f6
-.*: b3 ed 00 26 [ ]*eextr %r2,%f6
+.*: b3 ed 00 21 [ ]*eextr %r2,%f1
.*: b3 e7 00 26 [ ]*esdtr %r2,%f6
-.*: b3 ef 00 26 [ ]*esxtr %r2,%f6
+.*: b3 ef 00 21 [ ]*esxtr %r2,%f1
.*: b3 f6 20 64 [ ]*iedtr %f6,%f2,%r4
-.*: b3 fe 20 64 [ ]*iextr %f6,%f2,%r4
+.*: b3 fe 00 14 [ ]*iextr %f1,%f0,%r4
.*: b3 d6 00 62 [ ]*ltdtr %f6,%f2
-.*: b3 de 00 62 [ ]*ltxtr %f6,%f2
+.*: b3 de 00 54 [ ]*ltxtr %f5,%f4
.*: b3 d7 13 62 [ ]*fidtr %f6,1,%f2,3
-.*: b3 df 13 62 [ ]*fixtr %f6,1,%f2,3
+.*: b3 df 13 54 [ ]*fixtr %f5,1,%f4,3
.*: b2 bd 10 03 [ ]*lfas 3\(%r1\)
.*: b3 d4 01 62 [ ]*ldetr %f6,%f2,1
-.*: b3 dc 01 62 [ ]*lxdtr %f6,%f2,1
+.*: b3 dc 01 42 [ ]*lxdtr %f4,%f2,1
.*: b3 d5 13 62 [ ]*ledtr %f6,1,%f2,3
-.*: b3 dd 13 62 [ ]*ldxtr %f6,1,%f2,3
+.*: b3 dd 13 64 [ ]*ldxtr %f6,1,%f4,3
.*: b3 d0 40 62 [ ]*mdtr %f6,%f2,%f4
-.*: b3 d8 40 62 [ ]*mxtr %f6,%f2,%f4
+.*: b3 d8 40 98 [ ]*mxtr %f9,%f8,%f4
.*: b3 f5 21 64 [ ]*qadtr %f6,%f2,%f4,1
-.*: b3 fd 21 64 [ ]*qaxtr %f6,%f2,%f4,1
+.*: b3 fd 81 94 [ ]*qaxtr %f9,%f8,%f4,1
.*: b3 f7 21 64 [ ]*rrdtr %f6,%f2,%r4,1
-.*: b3 ff 21 64 [ ]*rrxtr %f6,%f2,%r4,1
+.*: b3 ff 81 94 [ ]*rrxtr %f9,%f8,%r4,1
.*: b2 b9 10 03 [ ]*srnmt 3\(%r1\)
.*: b3 85 00 20 [ ]*sfasr %r2
.*: ed 21 40 03 60 40 [ ]*sldt %f6,%f2,3\(%r1,%r4\)
-.*: ed 21 40 03 60 48 [ ]*slxt %f6,%f2,3\(%r1,%r4\)
+.*: ed 41 40 03 50 48 [ ]*slxt %f5,%f4,3\(%r1,%r4\)
.*: ed 21 40 03 60 41 [ ]*srdt %f6,%f2,3\(%r1,%r4\)
-.*: ed 21 40 03 60 49 [ ]*srxt %f6,%f2,3\(%r1,%r4\)
+.*: ed 41 40 03 50 49 [ ]*srxt %f5,%f4,3\(%r1,%r4\)
.*: b3 d3 40 62 [ ]*sdtr %f6,%f2,%f4
-.*: b3 db 40 62 [ ]*sxtr %f6,%f2,%f4
+.*: b3 db 40 51 [ ]*sxtr %f5,%f1,%f4
.*: ed 61 20 03 00 50 [ ]*tdcet %f6,3\(%r1,%r2\)
.*: ed 61 20 03 00 54 [ ]*tdcdt %f6,3\(%r1,%r2\)
-.*: ed 61 20 03 00 58 [ ]*tdcxt %f6,3\(%r1,%r2\)
+.*: ed 51 20 03 00 58 [ ]*tdcxt %f5,3\(%r1,%r2\)
.*: ed 61 20 03 00 51 [ ]*tdget %f6,3\(%r1,%r2\)
.*: ed 61 20 03 00 55 [ ]*tdgdt %f6,3\(%r1,%r2\)
-.*: ed 61 20 03 00 59 [ ]*tdgxt %f6,3\(%r1,%r2\)
+.*: ed 51 20 03 00 59 [ ]*tdgxt %f5,3\(%r1,%r2\)
.*: 01 0a [ ]*pfpo
.*: c8 31 10 0a 20 14 [ ]*ectg 10\(%r1\),20\(%r2\),%r3
.*: c8 32 10 0a 20 14 [ ]*csst 10\(%r1\),20\(%r2\),%r3
Index: gas/testsuite/gas/s390/zarch-z9-ec.s
===================================================================
--- gas/testsuite/gas/s390/zarch-z9-ec.s.orig
+++ gas/testsuite/gas/s390/zarch-z9-ec.s
@@ -7,62 +7,62 @@ foo:
ldgr %f6,%r2
lgdr %r2,%f6
adtr %f6,%f2,%f4
- axtr %f6,%f2,%f4
+ axtr %f8,%f9,%f4
cdtr %f6,%f2
- cxtr %f6,%f2
+ cxtr %f1,%f0
kdtr %f6,%f2
kxtr %f6,%f2
cedtr %f6,%f2
- cextr %f6,%f2
+ cextr %f1,%f0
cdgtr %f6,%r2
- cxgtr %f6,%r2
+ cxgtr %f1,%r2
cdstr %f6,%r2
cxstr %f6,%r2
cdutr %f6,%r2
- cxutr %f6,%r2
+ cxutr %f1,%r2
cgdtr %r2,1,%f6
- cgxtr %r2,1,%f6
+ cgxtr %r2,1,%f1
csdtr %r2,%f6
- csxtr %r2,%f6
+ csxtr %r2,%f1
cudtr %r2,%f6
- cuxtr %r2,%f6
+ cuxtr %r2,%f1
ddtr %f6,%f2,%f4
- dxtr %f6,%f2,%f4
+ dxtr %f1,%f0,%f4
eedtr %r2,%f6
- eextr %r2,%f6
+ eextr %r2,%f1
esdtr %r2,%f6
- esxtr %r2,%f6
+ esxtr %r2,%f1
iedtr %f6,%f2,%r4
- iextr %f6,%f2,%r4
+ iextr %f1,%f0,%r4
ltdtr %f6,%f2
- ltxtr %f6,%f2
+ ltxtr %f5,%f4
fidtr %f6,1,%f2,3
- fixtr %f6,1,%f2,3
+ fixtr %f5,1,%f4,3
lfas 3(%r1)
ldetr %f6,%f2,1
- lxdtr %f6,%f2,1
+ lxdtr %f4,%f2,1
ledtr %f6,1,%f2,3
- ldxtr %f6,1,%f2,3
+ ldxtr %f6,1,%f4,3
mdtr %f6,%f2,%f4
- mxtr %f6,%f2,%f4
+ mxtr %f9,%f8,%f4
qadtr %f6,%f2,%f4,1
- qaxtr %f6,%f2,%f4,1
+ qaxtr %f9,%f8,%f4,1
rrdtr %f6,%f2,%r4,1
- rrxtr %f6,%f2,%r4,1
+ rrxtr %f9,%f8,%r4,1
srnmt 3(%r1)
sfasr %r2
sldt %f6,%f2,3(%r1,%r4)
- slxt %f6,%f2,3(%r1,%r4)
+ slxt %f5,%f4,3(%r1,%r4)
srdt %f6,%f2,3(%r1,%r4)
- srxt %f6,%f2,3(%r1,%r4)
+ srxt %f5,%f4,3(%r1,%r4)
sdtr %f6,%f2,%f4
- sxtr %f6,%f2,%f4
+ sxtr %f5,%f1,%f4
tdcet %f6,3(%r1,%r2)
tdcdt %f6,3(%r1,%r2)
- tdcxt %f6,3(%r1,%r2)
+ tdcxt %f5,3(%r1,%r2)
tdget %f6,3(%r1,%r2)
tdgdt %f6,3(%r1,%r2)
- tdgxt %f6,3(%r1,%r2)
+ tdgxt %f5,3(%r1,%r2)
pfpo
ectg 10(%r1),20(%r2),%r3
csst 10(%r1),20(%r2),%r3
Index: opcodes/s390-opc.txt
===================================================================
--- opcodes/s390-opc.txt.orig
+++ opcodes/s390-opc.txt
@@ -551,7 +551,7 @@ e30000000090 llgc RXE_RRRD "load logical
e30000000091 llgh RXE_RRRD "load logical halfword" z900 zarch
eb000000001c rllg RSE_RRRD "rotate left single logical 64" z900 zarch
eb000000001d rll RSE_RRRD "rotate left single logical 32" z900 esa,zarch
-b369 cxr RRE_FF "compare extended hfp" g5 esa,zarch
+b369 cxr RRE_FEFE "compare extended hfp" g5 esa,zarch
b3b6 cxfr RRE_FER "convert from fixed 32 to extended hfp" g5 esa,zarch
b3b5 cdfr RRE_FR "convert from fixed 32 to long hfp" g5 esa,zarch
b3b4 cefr RRE_FR "convert from fixed 32 to short hfp" g5 esa,zarch