This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH 3/5] Add support for SPARC T4 crypto instructions.
- From: David Miller <davem at davemloft dot net>
- To: binutils at sourceware dot org
- Date: Thu, 19 Apr 2012 19:59:29 -0400 (EDT)
- Subject: [PATCH 3/5] Add support for SPARC T4 crypto instructions.
include/opcode/
* sparc.h: Document new arg code' )' for crypto RS3 immediates.
opcodes/
* sparc-dis.c (print_insn_sparc): Handle ')'.
* sparc-opc.c (sparc_opcodes): Add crypto instructions.
gas/
* config/tc-sparc.c (sparc_ip): Handle ')'. Accept instruction
names containing "_".
(sparc_arch_table): Add sparc4, v8pluse, and v9e. Add crypto
hwcap masks to v8plusv and v9v.
gas/testsuite/
* gas/sparc/crypto.s: New file.
* gas/sparc/crypto.d: New file.
* gas/sparc/sparc.exp: Run crypto test.
---
gas/config/tc-sparc.c | 50 +++++++++++++-
gas/testsuite/gas/sparc/crypto.d | 132 +++++++++++++++++++++++++++++++++++++
gas/testsuite/gas/sparc/crypto.s | 125 +++++++++++++++++++++++++++++++++++
gas/testsuite/gas/sparc/sparc.exp | 1 +
include/opcode/sparc.h | 1 +
opcodes/sparc-dis.c | 4 ++
opcodes/sparc-opc.c | 29 ++++++++
7 files changed, 339 insertions(+), 3 deletions(-)
create mode 100644 gas/testsuite/gas/sparc/crypto.d
create mode 100644 gas/testsuite/gas/sparc/crypto.s
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index 37bbbdd..f2f0ae8 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -245,6 +245,7 @@ static struct sparc_arch {
{ "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
{ "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
{ "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
+ { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
{ "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
{ "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
{ "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
@@ -254,13 +255,15 @@ static struct sparc_arch {
{ "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
{ "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
{ "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
- { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING },
+ { "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
+ { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
{ "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
{ "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
{ "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
{ "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
{ "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
- { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING },
+ { "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
+ { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C },
/* This exists to allow configure.in/Makefile.in to pass one
value to specify both the default machine and default word size. */
{ "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
@@ -1487,7 +1490,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
{
do
++s;
- while (ISLOWER (*s) || ISDIGIT (*s));
+ while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_');
}
switch (*s)
@@ -1799,6 +1802,47 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
the_insn.reloc = BFD_RELOC_SPARC_10;
goto immediate;
+ case ')':
+ if (*s == ' ')
+ s++;
+ if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2]))
+ || ISDIGIT (*s))
+ {
+ long num = 0;
+
+ if (s[0] == '0' && s[1] == 'x')
+ {
+ s += 2;
+ while (ISXDIGIT (*s))
+ {
+ num <<= 4;
+ num |= hex_value (*s);
+ ++s;
+ }
+ }
+ else
+ {
+ while (ISDIGIT (*s))
+ {
+ num = num * 10 + *s - '0';
+ ++s;
+ }
+ }
+ if (num < 0 || num > 31)
+ {
+ error_message = _(": crypto immediate must be between 0 and 31");
+ goto error;
+ }
+
+ opcode |= RS3 (num);
+ continue;
+ }
+ else
+ {
+ error_message = _(": expecting crypto immediate");
+ goto error;
+ }
+
case 'X':
/* V8 systems don't understand BFD_RELOC_SPARC_5. */
if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
diff --git a/gas/testsuite/gas/sparc/crypto.d b/gas/testsuite/gas/sparc/crypto.d
new file mode 100644
index 0000000..734317d
--- /dev/null
+++ b/gas/testsuite/gas/sparc/crypto.d
@@ -0,0 +1,132 @@
+#as: -Av9v
+#objdump: -dr
+#name: sparc CRYPTO
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+ 0: 81 b0 28 00 md5
+ 4: 81 b0 28 20 sha1
+ 8: 81 b0 28 40 sha256
+ c: 81 b0 28 60 sha512
+ 10: 8d b0 a8 e4 crc32c %f2, %f4, %f6
+ 14: 91 b1 26 06 aes_kexpand0 %f4, %f6, %f8
+ 18: 94 41 8f 08 aes_kexpand1 %f6, %f8, 0x7, %f10
+ 1c: 94 41 8d 08 aes_kexpand1 %f6, %f8, 0x6, %f10
+ 20: 99 b2 26 2a aes_kexpand2 %f8, %f10, %f12
+ 24: a0 42 9c 0c aes_eround01 %f10, %f12, %f14, %f16
+ 28: a4 43 20 2e aes_eround23 %f12, %f14, %f16, %f18
+ 2c: a8 43 a4 50 aes_dround01 %f14, %f16, %f18, %f20
+ 30: ac 44 28 72 aes_dround23 %f16, %f18, %f20, %f22
+ 34: b0 44 ac 94 aes_eround01_l %f18, %f20, %f22, %f24
+ 38: b4 45 30 b6 aes_eround23_l %f20, %f22, %f24, %f26
+ 3c: b8 45 b4 d8 aes_dround01_l %f22, %f24, %f26, %f28
+ 40: bc 46 38 fa aes_dround23_l %f24, %f26, %f28, %f30
+ 44: 87 b0 66 80 des_ip %f32, %f34
+ 48: 8b b0 e6 a0 des_iip %f34, %f36
+ 4c: 8f b1 66 c7 des_kexpand %f36, 7, %f38
+ 50: 9a 41 d7 29 des_round %f38, %f40, %f42, %f44
+ 54: 9f b2 e7 0d kasumi_fi_fi %f42, %f44, %f46
+ 58: a6 43 63 4f kasumi_fl_xor %f44, %f46, %f48, %f50
+ 5c: aa 43 e7 71 kasumi_fi_xor %f46, %f48, %f50, %f52
+ 60: af b4 e7 95 camellia_fi %f50, %f52, %f54
+ 64: b3 b5 67 b7 camellia_fli %f52, %f54, %f56
+ 68: ba 45 f7 99 camellia_f %f54, %f56, %f58, %f60
+ 6c: 81 b0 29 00 mpmul 0
+ 70: 81 b0 29 01 mpmul 1
+ 74: 81 b0 29 02 mpmul 2
+ 78: 81 b0 29 03 mpmul 3
+ 7c: 81 b0 29 04 mpmul 4
+ 80: 81 b0 29 05 mpmul 5
+ 84: 81 b0 29 06 mpmul 6
+ 88: 81 b0 29 07 mpmul 7
+ 8c: 81 b0 29 08 mpmul 8
+ 90: 81 b0 29 09 mpmul 9
+ 94: 81 b0 29 0a mpmul 0xa
+ 98: 81 b0 29 0b mpmul 0xb
+ 9c: 81 b0 29 0c mpmul 0xc
+ a0: 81 b0 29 0d mpmul 0xd
+ a4: 81 b0 29 0e mpmul 0xe
+ a8: 81 b0 29 0f mpmul 0xf
+ ac: 81 b0 29 10 mpmul 0x10
+ b0: 81 b0 29 11 mpmul 0x11
+ b4: 81 b0 29 12 mpmul 0x12
+ b8: 81 b0 29 13 mpmul 0x13
+ bc: 81 b0 29 14 mpmul 0x14
+ c0: 81 b0 29 15 mpmul 0x15
+ c4: 81 b0 29 16 mpmul 0x16
+ c8: 81 b0 29 17 mpmul 0x17
+ cc: 81 b0 29 18 mpmul 0x18
+ d0: 81 b0 29 19 mpmul 0x19
+ d4: 81 b0 29 1a mpmul 0x1a
+ d8: 81 b0 29 1b mpmul 0x1b
+ dc: 81 b0 29 1c mpmul 0x1c
+ e0: 81 b0 29 1d mpmul 0x1d
+ e4: 81 b0 29 1e mpmul 0x1e
+ e8: 81 b0 29 1f mpmul 0x1f
+ ec: 81 b0 29 20 montmul 0
+ f0: 81 b0 29 21 montmul 1
+ f4: 81 b0 29 22 montmul 2
+ f8: 81 b0 29 23 montmul 3
+ fc: 81 b0 29 24 montmul 4
+ 100: 81 b0 29 25 montmul 5
+ 104: 81 b0 29 26 montmul 6
+ 108: 81 b0 29 27 montmul 7
+ 10c: 81 b0 29 28 montmul 8
+ 110: 81 b0 29 29 montmul 9
+ 114: 81 b0 29 2a montmul 0xa
+ 118: 81 b0 29 2b montmul 0xb
+ 11c: 81 b0 29 2c montmul 0xc
+ 120: 81 b0 29 2d montmul 0xd
+ 124: 81 b0 29 2e montmul 0xe
+ 128: 81 b0 29 2f montmul 0xf
+ 12c: 81 b0 29 30 montmul 0x10
+ 130: 81 b0 29 31 montmul 0x11
+ 134: 81 b0 29 32 montmul 0x12
+ 138: 81 b0 29 33 montmul 0x13
+ 13c: 81 b0 29 34 montmul 0x14
+ 140: 81 b0 29 35 montmul 0x15
+ 144: 81 b0 29 36 montmul 0x16
+ 148: 81 b0 29 37 montmul 0x17
+ 14c: 81 b0 29 38 montmul 0x18
+ 150: 81 b0 29 39 montmul 0x19
+ 154: 81 b0 29 3a montmul 0x1a
+ 158: 81 b0 29 3b montmul 0x1b
+ 15c: 81 b0 29 3c montmul 0x1c
+ 160: 81 b0 29 3d montmul 0x1d
+ 164: 81 b0 29 3e montmul 0x1e
+ 168: 81 b0 29 3f montmul 0x1f
+ 16c: 81 b0 29 40 montsqr 0
+ 170: 81 b0 29 41 montsqr 1
+ 174: 81 b0 29 42 montsqr 2
+ 178: 81 b0 29 43 montsqr 3
+ 17c: 81 b0 29 44 montsqr 4
+ 180: 81 b0 29 45 montsqr 5
+ 184: 81 b0 29 46 montsqr 6
+ 188: 81 b0 29 47 montsqr 7
+ 18c: 81 b0 29 48 montsqr 8
+ 190: 81 b0 29 49 montsqr 9
+ 194: 81 b0 29 4a montsqr 0xa
+ 198: 81 b0 29 4b montsqr 0xb
+ 19c: 81 b0 29 4c montsqr 0xc
+ 1a0: 81 b0 29 4d montsqr 0xd
+ 1a4: 81 b0 29 4e montsqr 0xe
+ 1a8: 81 b0 29 4f montsqr 0xf
+ 1ac: 81 b0 29 50 montsqr 0x10
+ 1b0: 81 b0 29 51 montsqr 0x11
+ 1b4: 81 b0 29 52 montsqr 0x12
+ 1b8: 81 b0 29 53 montsqr 0x13
+ 1bc: 81 b0 29 54 montsqr 0x14
+ 1c0: 81 b0 29 55 montsqr 0x15
+ 1c4: 81 b0 29 56 montsqr 0x16
+ 1c8: 81 b0 29 57 montsqr 0x17
+ 1cc: 81 b0 29 58 montsqr 0x18
+ 1d0: 81 b0 29 59 montsqr 0x19
+ 1d4: 81 b0 29 5a montsqr 0x1a
+ 1d8: 81 b0 29 5b montsqr 0x1b
+ 1dc: 81 b0 29 5c montsqr 0x1c
+ 1e0: 81 b0 29 5d montsqr 0x1d
+ 1e4: 81 b0 29 5e montsqr 0x1e
+ 1e8: 81 b0 29 5f montsqr 0x1f
diff --git a/gas/testsuite/gas/sparc/crypto.s b/gas/testsuite/gas/sparc/crypto.s
new file mode 100644
index 0000000..217a742
--- /dev/null
+++ b/gas/testsuite/gas/sparc/crypto.s
@@ -0,0 +1,125 @@
+# Test CRYPTO instructions
+ .text
+ md5
+ sha1
+ sha256
+ sha512
+ crc32c %f2, %f4, %f6
+ aes_kexpand0 %f4, %f6, %f8
+ aes_kexpand1 %f6, %f8, 0x7, %f10
+ aes_kexpand1 %f6, %f8, 6, %f10
+ aes_kexpand2 %f8, %f10, %f12
+ aes_eround01 %f10, %f12, %f14, %f16
+ aes_eround23 %f12, %f14, %f16, %f18
+ aes_dround01 %f14, %f16, %f18, %f20
+ aes_dround23 %f16, %f18, %f20, %f22
+ aes_eround01_l %f18, %f20, %f22, %f24
+ aes_eround23_l %f20, %f22, %f24, %f26
+ aes_dround01_l %f22, %f24, %f26, %f28
+ aes_dround23_l %f24, %f26, %f28, %f30
+ des_ip %f32, %f34
+ des_iip %f34, %f36
+ des_kexpand %f36, 7, %f38
+ des_round %f38, %f40, %f42, %f44
+ kasumi_fi_fi %f42, %f44, %f46
+ kasumi_fl_xor %f44, %f46, %f48, %f50
+ kasumi_fi_xor %f46, %f48, %f50, %f52
+ camellia_fi %f50, %f52, %f54
+ camellia_fli %f52, %f54, %f56
+ camellia_f %f54, %f56, %f58, %f60
+ mpmul 0
+ mpmul 1
+ mpmul 2
+ mpmul 3
+ mpmul 4
+ mpmul 5
+ mpmul 6
+ mpmul 7
+ mpmul 8
+ mpmul 9
+ mpmul 10
+ mpmul 11
+ mpmul 12
+ mpmul 13
+ mpmul 14
+ mpmul 15
+ mpmul 16
+ mpmul 17
+ mpmul 18
+ mpmul 19
+ mpmul 20
+ mpmul 21
+ mpmul 22
+ mpmul 23
+ mpmul 24
+ mpmul 25
+ mpmul 26
+ mpmul 27
+ mpmul 28
+ mpmul 29
+ mpmul 30
+ mpmul 31
+ montmul 0
+ montmul 1
+ montmul 2
+ montmul 3
+ montmul 4
+ montmul 5
+ montmul 6
+ montmul 7
+ montmul 8
+ montmul 9
+ montmul 10
+ montmul 11
+ montmul 12
+ montmul 13
+ montmul 14
+ montmul 15
+ montmul 16
+ montmul 17
+ montmul 18
+ montmul 19
+ montmul 20
+ montmul 21
+ montmul 22
+ montmul 23
+ montmul 24
+ montmul 25
+ montmul 26
+ montmul 27
+ montmul 28
+ montmul 29
+ montmul 30
+ montmul 31
+ montsqr 0
+ montsqr 1
+ montsqr 2
+ montsqr 3
+ montsqr 4
+ montsqr 5
+ montsqr 6
+ montsqr 7
+ montsqr 8
+ montsqr 9
+ montsqr 10
+ montsqr 11
+ montsqr 12
+ montsqr 13
+ montsqr 14
+ montsqr 15
+ montsqr 16
+ montsqr 17
+ montsqr 18
+ montsqr 19
+ montsqr 20
+ montsqr 21
+ montsqr 22
+ montsqr 23
+ montsqr 24
+ montsqr 25
+ montsqr 26
+ montsqr 27
+ montsqr 28
+ montsqr 29
+ montsqr 30
+ montsqr 31
diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index 65e84ce..f2ad181 100644
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -62,6 +62,7 @@ if [istarget sparc*-*-*] {
run_dump_test "pc2210"
run_dump_test "hpcvis3"
run_dump_test "ima"
+ run_dump_test "crypto"
run_list_test "pr4587" ""
}
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index 5d4d3c9..b1c5e42 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -224,6 +224,7 @@ typedef struct sparc_opcode
_ Ancillary state register in rd (v9a)
/ Ancillary state register in rs1 (v9a)
( entire floating point state register (%efsr)
+ ) 5 bit immediate placed in RS3 field
= 2+8 bit PC relative immediate. (v9) */
#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index 7857e4c..bda1b0d 100644
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -704,6 +704,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
}
break;
+ case ')': /* 5 bit unsigned immediate from RS3. */
+ (info->fprintf_func) (stream, "%#x", X_RS3 (insn));
+ break;
+
case 'X': /* 5 bit unsigned immediate. */
case 'Y': /* 6 bit unsigned immediate. */
{
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 416c809..2ae6fd2 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -1907,6 +1907,35 @@ SLCBCC("cbnefr", 15),
{ "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, v9b },
{ "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, v9b },
{ "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, v9b },
+{"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
+{ "des_ip", F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT, HWCAP_DES, v9b },
+{ "des_iip", F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, v9b },
+{ "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT, HWCAP_DES, v9b },
+{"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT, HWCAP_KASUMI, v9b },
+{ "camellia_fi",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
+{"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
+{ "md5", F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT, HWCAP_MD5, v9b },
+{ "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, v9b },
+{ "sha256", F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT, HWCAP_SHA256, v9b },
+{ "sha512", F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT, HWCAP_SHA512, v9b },
+{ "crc32c", F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT, HWCAP_CRC32C, v9b },
+{ "mpmul", F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, v9b },
+{ "montmul", F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, v9b },
+{ "montsqr", F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, v9b },
+{"aes_eround01", F2(2, 0x19)|OPF_LOW4(0), F2(~2, ~0x19)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_eround23", F2(2, 0x19)|OPF_LOW4(1), F2(~2, ~0x19)|OPF_LOW4(~1), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_dround01", F2(2, 0x19)|OPF_LOW4(2), F2(~2, ~0x19)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_dround23", F2(2, 0x19)|OPF_LOW4(3), F2(~2, ~0x19)|OPF_LOW4(~3), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_eround01_l",F2(2, 0x19)|OPF_LOW4(4), F2(~2, ~0x19)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_eround23_l",F2(2, 0x19)|OPF_LOW4(5), F2(~2, ~0x19)|OPF_LOW4(~5), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_dround01_l",F2(2, 0x19)|OPF_LOW4(6), F2(~2, ~0x19)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_dround23_l",F2(2, 0x19)|OPF_LOW4(7), F2(~2, ~0x19)|OPF_LOW4(~7), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
+{"aes_kexpand1", F2(2, 0x19)|OPF_LOW4(8), F2(~2, ~0x19)|OPF_LOW4(~8), "v,B,),H", F_FLOAT, HWCAP_AES, v9b },
+{"des_round", F2(2, 0x19)|OPF_LOW4(9), F2(~2, ~0x19)|OPF_LOW4(~9), "v,B,5,H", F_FLOAT, HWCAP_DES, v9b },
+{"kasumi_fl_xor", F2(2, 0x19)|OPF_LOW4(10), F2(~2, ~0x19)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
+{"kasumi_fi_xor", F2(2, 0x19)|OPF_LOW4(11), F2(~2, ~0x19)|OPF_LOW4(~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
+{"camellia_f", F2(2, 0x19)|OPF_LOW4(12), F2(~2, ~0x19)|OPF_LOW4(~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
{ "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, v9b },
{ "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, v9b },
{ "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, v9b },
--
1.7.9.5