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Re: [PATCH] MIPS: Opcode membership proposal
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: "Maciej W. Rozycki" <macro at codesourcery dot com>
- Cc: David Daney <ddaney at caviumnetworks dot com>, Andrew Pinski <andrew dot pinski at caviumnetworks dot com>, <binutils at sourceware dot org>
- Date: Sun, 12 Aug 2012 19:32:38 +0100
- Subject: Re: [PATCH] MIPS: Opcode membership proposal
- References: <alpine.DEB.1.10.1012181108290.4142@tp.orcam.me.uk> <alpine.DEB.1.10.1110311233290.28657@tp.orcam.me.uk> <87obway4f5.fsf@firetop.home> <alpine.DEB.1.10.1208092012040.20608@tp.orcam.me.uk>
"Maciej W. Rozycki" <macro@codesourcery.com> writes:
> On Thu, 17 Nov 2011, Richard Sandiford wrote:
>
>> > @@ -830,37 +833,38 @@ static const unsigned int mips_isa_table
>> > ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
>> > test, or zero if no CPU specific ISA test is desired. */
>> >
>> > -#define OPCODE_IS_MEMBER(insn, isa, cpu) \
>> > - (((isa & INSN_ISA_MASK) != 0 \
>> > - && ((insn)->membership & INSN_ISA_MASK) != 0 \
>> > - && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
>> > - (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
>> > - || ((isa & ~INSN_ISA_MASK) \
>> > - & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
>> > - || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
>> > - || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
>> > - || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
>> > - || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
>> > - || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
>> > - || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
>> > - || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
>> > - || cpu == CPU_R16000) \
>> > - && ((insn)->membership & INSN_10000) != 0) \
>> > - || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
>> > - || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
>> > - || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
>> > - || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
>> > - || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
>> > - || (cpu == CPU_LOONGSON_2E \
>> > - && ((insn)->membership & INSN_LOONGSON_2E) != 0) \
>> > - || (cpu == CPU_LOONGSON_2F \
>> > - && ((insn)->membership & INSN_LOONGSON_2F) != 0) \
>> > - || (cpu == CPU_LOONGSON_3A \
>> > - && ((insn)->membership & INSN_LOONGSON_3A) != 0) \
>> > - || (cpu == CPU_OCTEON \
>> > - && ((insn)->membership & INSN_OCTEON) != 0) \
>> > - || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
>> > - || 0) /* Please keep this term for easier source merging. */
>> > +#define OPCODE_IS_MEMBER(insn, isa, cpu) \
>> > + ((((isa & INSN_ISA_MASK) != 0 \
>> > + && ((insn)->membership & INSN_ISA_MASK) != 0 \
>> > + && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
>> > + (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
>> > + || ((isa & ~INSN_ISA_MASK) \
>> > + & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
>> > + || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
>> > + || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
>> > + || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
>> > + || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
>> > + || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
>> > + || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
>> > + || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
>> > + || cpu == CPU_R16000) \
>> > + && ((insn)->membership & INSN_10000) != 0) \
>> > + || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
>> > + || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
>> > + || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
>> > + || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
>> > + || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
>> > + || (cpu == CPU_LOONGSON_2E \
>> > + && ((insn)->membership & INSN_LOONGSON_2E) != 0) \
>> > + || (cpu == CPU_LOONGSON_2F \
>> > + && ((insn)->membership & INSN_LOONGSON_2F) != 0) \
>> > + || (cpu == CPU_LOONGSON_3A \
>> > + && ((insn)->membership & INSN_LOONGSON_3A) != 0) \
>> > + || (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0) \
>> > + || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
>> > + || 0) /* Please keep this term for easier source merging. */ \
>> > + && ((cpu != CPU_OCTEON || ((insn)->exclusions & CPU_OCTEON) == 0) \
>>
>> Looks like a typo for "((insn)->exclusions & INSN_OCTEON) == 0".
>
> Hmm, where's the typo? That's supposed to be true as long as the CPU is
> other than Octeon or the Octeon exclusion bit is zero. Did I get that
> wrong?
The typo is in the last line I quoted:
>> > + && ((cpu != CPU_OCTEON || ((insn)->exclusions & CPU_OCTEON) == 0)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
CPU_OCTEON is an enum value (6501), not a bitmask value. As I say,
it looked like it should be "((insn)->exclusions & INSN_OCTEON) == 0"
instead.
Patch is OK.
Richard