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Fix powerpc -m32 -mpowerpc64 ABI related bugs
- From: Alan Modra <amodra at gmail dot com>
- To: binutils at sourceware dot org
- Date: Fri, 26 Oct 2012 14:13:57 +1030
- Subject: Fix powerpc -m32 -mpowerpc64 ABI related bugs
This adds workarounds for a ppc32 ABI deficiency, lack of proper
DS-form relocations. The instructions that use a DS-form offset are
ld, ldu, lwa, std, stdu, stq, lfdp, and stfdp, all 64-bit processor
insns. They aren't normally used in 32-bit mode; You'll only hit a
problem if compiling with -m32 -mpowerpc64.
DS-form insns differ from D-form insns in that the low two bits of the
insn are not part of the offset. The effect of using incorrect D-form
relocations on the insns is that when the reloc is applied the low two
bits are overwritten, for example, changing an lwa instruction to an
ld instruction. This happens both in ld and as. See
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=27619
So what I've done here is enable the DS-form relocations internally in
gas (reloc_type_lookup and md_assemble patches), which stops gas
itself from trashing the low 2 bits of these insns. The
relocate_section patch stops ld trashing them.
bfd/
PR target/14758
* elf32-ppc.c (ppc_elf_reloc_type_lookup): Decode ppc64 _DS
bfd_reloc values. Map to corresponding D-form relocs.
(is_insn_ds_form, is_insn_qs_form): New functions.
(ppc_elf_relocate_section): Validate insn with DS-form or DQ-form
fields using D-form reloc.
opcodes/
* ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
gas/
PR target/14758
* config/tc-ppc.c (ppc_setup_opcodes): Fix comment.
(md_assemble): Translate to _DS relocs for ppc32 as well as ppc64.
(tc_gen_reloc): Handle _DS relocs in ppc32 mode.
gas/testsuite/
* gas/ppc/power4.s: Fix invalid lq offsets.
* gas/ppc/power4.d: Update.
Index: bfd/elf32-ppc.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-ppc.c,v
retrieving revision 1.320
diff -u -p -r1.320 elf32-ppc.c
--- bfd/elf32-ppc.c 28 Aug 2012 20:17:55 -0000 1.320
+++ bfd/elf32-ppc.c 26 Oct 2012 03:19:18 -0000
@@ -1815,7 +1815,9 @@ ppc_elf_reloc_type_lookup (bfd *abfd ATT
case BFD_RELOC_NONE: r = R_PPC_NONE; break;
case BFD_RELOC_32: r = R_PPC_ADDR32; break;
case BFD_RELOC_PPC_BA26: r = R_PPC_ADDR24; break;
+ case BFD_RELOC_PPC64_ADDR16_DS:
case BFD_RELOC_16: r = R_PPC_ADDR16; break;
+ case BFD_RELOC_PPC64_ADDR16_LO_DS:
case BFD_RELOC_LO16: r = R_PPC_ADDR16_LO; break;
case BFD_RELOC_HI16: r = R_PPC_ADDR16_HI; break;
case BFD_RELOC_HI16_S: r = R_PPC_ADDR16_HA; break;
@@ -1826,7 +1828,9 @@ ppc_elf_reloc_type_lookup (bfd *abfd ATT
case BFD_RELOC_PPC_B16: r = R_PPC_REL14; break;
case BFD_RELOC_PPC_B16_BRTAKEN: r = R_PPC_REL14_BRTAKEN; break;
case BFD_RELOC_PPC_B16_BRNTAKEN: r = R_PPC_REL14_BRNTAKEN; break;
+ case BFD_RELOC_PPC64_GOT16_DS:
case BFD_RELOC_16_GOTOFF: r = R_PPC_GOT16; break;
+ case BFD_RELOC_PPC64_GOT16_LO_DS:
case BFD_RELOC_LO16_GOTOFF: r = R_PPC_GOT16_LO; break;
case BFD_RELOC_HI16_GOTOFF: r = R_PPC_GOT16_HI; break;
case BFD_RELOC_HI16_S_GOTOFF: r = R_PPC_GOT16_HA; break;
@@ -1837,26 +1841,34 @@ ppc_elf_reloc_type_lookup (bfd *abfd ATT
case BFD_RELOC_32_PCREL: r = R_PPC_REL32; break;
case BFD_RELOC_32_PLTOFF: r = R_PPC_PLT32; break;
case BFD_RELOC_32_PLT_PCREL: r = R_PPC_PLTREL32; break;
+ case BFD_RELOC_PPC64_PLT16_LO_DS:
case BFD_RELOC_LO16_PLTOFF: r = R_PPC_PLT16_LO; break;
case BFD_RELOC_HI16_PLTOFF: r = R_PPC_PLT16_HI; break;
case BFD_RELOC_HI16_S_PLTOFF: r = R_PPC_PLT16_HA; break;
case BFD_RELOC_GPREL16: r = R_PPC_SDAREL16; break;
+ case BFD_RELOC_PPC64_SECTOFF_DS:
case BFD_RELOC_16_BASEREL: r = R_PPC_SECTOFF; break;
+ case BFD_RELOC_PPC64_SECTOFF_LO_DS:
case BFD_RELOC_LO16_BASEREL: r = R_PPC_SECTOFF_LO; break;
case BFD_RELOC_HI16_BASEREL: r = R_PPC_SECTOFF_HI; break;
case BFD_RELOC_HI16_S_BASEREL: r = R_PPC_SECTOFF_HA; break;
case BFD_RELOC_CTOR: r = R_PPC_ADDR32; break;
+ case BFD_RELOC_PPC64_TOC16_DS:
case BFD_RELOC_PPC_TOC16: r = R_PPC_TOC16; break;
case BFD_RELOC_PPC_TLS: r = R_PPC_TLS; break;
case BFD_RELOC_PPC_TLSGD: r = R_PPC_TLSGD; break;
case BFD_RELOC_PPC_TLSLD: r = R_PPC_TLSLD; break;
case BFD_RELOC_PPC_DTPMOD: r = R_PPC_DTPMOD32; break;
+ case BFD_RELOC_PPC64_TPREL16_DS:
case BFD_RELOC_PPC_TPREL16: r = R_PPC_TPREL16; break;
+ case BFD_RELOC_PPC64_TPREL16_LO_DS:
case BFD_RELOC_PPC_TPREL16_LO: r = R_PPC_TPREL16_LO; break;
case BFD_RELOC_PPC_TPREL16_HI: r = R_PPC_TPREL16_HI; break;
case BFD_RELOC_PPC_TPREL16_HA: r = R_PPC_TPREL16_HA; break;
case BFD_RELOC_PPC_TPREL: r = R_PPC_TPREL32; break;
+ case BFD_RELOC_PPC64_DTPREL16_DS:
case BFD_RELOC_PPC_DTPREL16: r = R_PPC_DTPREL16; break;
+ case BFD_RELOC_PPC64_DTPREL16_LO_DS:
case BFD_RELOC_PPC_DTPREL16_LO: r = R_PPC_DTPREL16_LO; break;
case BFD_RELOC_PPC_DTPREL16_HI: r = R_PPC_DTPREL16_HI; break;
case BFD_RELOC_PPC_DTPREL16_HA: r = R_PPC_DTPREL16_HA; break;
@@ -7243,6 +7255,21 @@ _bfd_elf_ppc_at_tprel_transform (unsigne
return insn;
}
+static bfd_boolean
+is_insn_ds_form (unsigned int insn)
+{
+ return ((insn & (0x3f << 26)) == 58u << 26 /* ld,ldu,lwa */
+ || (insn & (0x3f << 26)) == 62u << 26 /* std,stdu,stq */
+ || (insn & (0x3f << 26)) == 57u << 26 /* lfdp */
+ || (insn & (0x3f << 26)) == 61u << 26 /* stfdp */);
+}
+
+static bfd_boolean
+is_insn_dq_form (unsigned int insn)
+{
+ return (insn & (0x3f << 26)) == 56u << 26; /* lq */
+}
+
/* The RELOCATE_SECTION function is called by the ELF backend linker
to handle the relocations for a section.
@@ -8788,6 +8815,54 @@ ppc_elf_relocate_section (bfd *output_bf
Bits 0:15 are not used. */
addend += 0x8000;
break;
+
+ case R_PPC_ADDR16:
+ case R_PPC_ADDR16_LO:
+ case R_PPC_GOT16:
+ case R_PPC_GOT16_LO:
+ case R_PPC_SDAREL16:
+ case R_PPC_SECTOFF:
+ case R_PPC_SECTOFF_LO:
+ case R_PPC_DTPREL16:
+ case R_PPC_DTPREL16_LO:
+ case R_PPC_TPREL16:
+ case R_PPC_TPREL16_LO:
+ case R_PPC_GOT_TLSGD16:
+ case R_PPC_GOT_TLSGD16_LO:
+ case R_PPC_GOT_TLSLD16:
+ case R_PPC_GOT_TLSLD16_LO:
+ case R_PPC_GOT_DTPREL16:
+ case R_PPC_GOT_DTPREL16_LO:
+ case R_PPC_GOT_TPREL16:
+ case R_PPC_GOT_TPREL16_LO:
+ {
+ /* The 32-bit ABI lacks proper relocations to deal with
+ certain 64-bit instructions. Prevent damage to bits
+ that make up part of the insn opcode. */
+ unsigned int insn, mask, lobit;
+
+ insn = bfd_get_32 (output_bfd, contents + rel->r_offset - d_offset);
+ mask = 0;
+ if (is_insn_ds_form (insn))
+ mask = 3;
+ else if (is_insn_dq_form (insn))
+ mask = 15;
+ else
+ break;
+ lobit = mask & (relocation + addend);
+ if (lobit != 0)
+ {
+ addend -= lobit;
+ info->callbacks->einfo
+ (_("%P: %H: error: %s against `%s' not a multiple of %u\n"),
+ input_bfd, input_section, rel->r_offset,
+ howto->name, sym_name, mask + 1);
+ bfd_set_error (bfd_error_bad_value);
+ ret = FALSE;
+ }
+ addend += insn & mask;
+ }
+ break;
}
#ifdef DEBUG
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.155
diff -u -p -r1.155 ppc-opc.c
--- opcodes/ppc-opc.c 22 Oct 2012 16:04:26 -0000 1.155
+++ opcodes/ppc-opc.c 26 Oct 2012 00:51:40 -0000
@@ -5726,7 +5726,7 @@ const struct powerpc_opcode powerpc_opco
{"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
{"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
-{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRTp, D, RA0}},
+{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRTp, DS, RA0}},
{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
{"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
@@ -5989,7 +5989,7 @@ const struct powerpc_opcode powerpc_opco
{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
-{"stfdp", OP(61), OP_MASK, POWER6, POWER7, {FRSp, D, RA0}},
+{"stfdp", OP(61), OP_MASK, POWER6, POWER7, {FRSp, DS, RA0}},
{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.185
diff -u -p -r1.185 tc-ppc.c
--- gas/config/tc-ppc.c 1 Aug 2012 13:46:56 -0000 1.185
+++ gas/config/tc-ppc.c 26 Oct 2012 03:19:18 -0000
@@ -1513,7 +1513,7 @@ insn_validate (const struct powerpc_opco
}
/* Insert opcodes and macros into hash tables. Called at startup and
- for .cpu pseudo. */
+ for .machine pseudo. */
static void
ppc_setup_opcodes (void)
@@ -3062,8 +3062,7 @@ md_assemble (char *str)
break;
}
- if (ppc_obj64
- && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0)
+ if ((operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0)
{
switch (reloc)
{
Index: gas/testsuite/gas/ppc/power4.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/power4.d,v
retrieving revision 1.8
diff -u -p -r1.8 power4.d
--- gas/testsuite/gas/ppc/power4.d 15 Aug 2012 21:25:21 -0000 1.8
+++ gas/testsuite/gas/ppc/power4.d 25 Oct 2012 23:54:53 -0000
@@ -10,23 +10,23 @@ start address 0x0+
Sections:
Idx Name +Size +VMA +LMA +File off +Algn
- +0 \.text +0+dc +0+ +0+ +.*
+ +0 \.text +0+c8 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
- +1 \.data +0+10 +0+ +0+ +.*
+ +1 \.data +0+20 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, DATA
+2 \.bss +0+ +0+ +0+ +.*
+ALLOC
- +3 \.toc +0+30 +0+ +0+ +.*
+ +3 \.toc +0+20 +0+ +0+ +.*
+CONTENTS, ALLOC, LOAD, RELOC, DATA
SYMBOL TABLE:
0+ l +d +\.text 0+ (|\.text)
0+ l +d +\.data 0+ (|\.data)
0+ l +d +\.bss 0+ (|\.bss)
0+ l +\.data 0+ dsym0
-0+8 l +\.data 0+ dsym1
+0+10 l +\.data 0+ dsym1
0+ l +d +\.toc 0+ (|\.toc)
-0+8 l +\.data 0+ usym0
-0+10 l +\.data 0+ usym1
+0+10 l +\.data 0+ usym0
+0+20 l +\.data 0+ usym1
0+ +\*UND\* 0+ esym0
0+ +\*UND\* 0+ esym1
@@ -34,77 +34,67 @@ SYMBOL TABLE:
Disassembly of section \.text:
0+ <\.text>:
- +0: e0 83 00 00 lq r4,0\(r3\)
- 2: R_PPC64_ADDR16_LO_DS \.data
- +4: e0 83 00 00 lq r4,0\(r3\)
- 6: R_PPC64_ADDR16_LO_DS \.data\+0x8
- +8: e0 83 00 00 lq r4,0\(r3\)
- a: R_PPC64_ADDR16_LO_DS \.data\+0x8
- +c: e0 83 00 10 lq r4,16\(r3\)
- e: R_PPC64_ADDR16_LO_DS \.data\+0x10
- +10: e0 83 00 00 lq r4,0\(r3\)
- 12: R_PPC64_ADDR16_LO_DS esym0
- +14: e0 83 00 00 lq r4,0\(r3\)
- 16: R_PPC64_ADDR16_LO_DS esym1
- +18: e0 82 00 00 lq r4,0\(r2\)
- 1a: R_PPC64_TOC16_DS \.toc
- +1c: e0 82 00 00 lq r4,0\(r2\)
- 1e: R_PPC64_TOC16_DS \.toc\+0x8
- +20: e0 82 00 10 lq r4,16\(r2\)
- 22: R_PPC64_TOC16_DS \.toc\+0x10
- +24: e0 82 00 10 lq r4,16\(r2\)
- 26: R_PPC64_TOC16_DS \.toc\+0x18
- +28: e0 82 00 20 lq r4,32\(r2\)
- 2a: R_PPC64_TOC16_DS \.toc\+0x20
- +2c: e0 82 00 20 lq r4,32\(r2\)
- 2e: R_PPC64_TOC16_DS \.toc\+0x28
- +30: e0 c2 00 20 lq r6,32\(r2\)
- 32: R_PPC64_TOC16_LO_DS \.toc\+0x28
- +34: e0 80 00 00 lq r4,0\(0\)
- 36: R_PPC64_ADDR16_LO_DS \.text
- +38: e0 c3 00 00 lq r6,0\(r3\)
- 3a: R_PPC64_GOT16_DS dsym0
- +3c: e0 c3 00 00 lq r6,0\(r3\)
- 3e: R_PPC64_GOT16_LO_DS dsym0
- +40: e0 c3 00 00 lq r6,0\(r3\)
- 42: R_PPC64_PLT16_LO_DS \.data
- +44: e0 c3 00 00 lq r6,0\(r3\)
- 46: R_PPC64_SECTOFF_DS \.data\+0x8
- +48: e0 c3 00 00 lq r6,0\(r3\)
- 4a: R_PPC64_SECTOFF_LO_DS \.data\+0x8
- +4c: e0 c4 00 10 lq r6,16\(r4\)
- +50: f8 c7 00 02 stq r6,0\(r7\)
- +54: f8 c7 00 12 stq r6,16\(r7\)
- +58: f8 c7 ff f2 stq r6,-16\(r7\)
- +5c: f8 c7 80 02 stq r6,-32768\(r7\)
- +60: f8 c7 7f f2 stq r6,32752\(r7\)
- +64: 00 00 02 00 attn
- +68: 7c 6f f1 20 mtcr r3
- +6c: 7c 6f f1 20 mtcr r3
- +70: 7c 68 11 20 mtcrf 129,r3
- +74: 7c 70 11 20 mtocrf 1,r3
- +78: 7c 70 21 20 mtocrf 2,r3
- +7c: 7c 70 41 20 mtocrf 4,r3
- +80: 7c 70 81 20 mtocrf 8,r3
- +84: 7c 71 01 20 mtocrf 16,r3
- +88: 7c 72 01 20 mtocrf 32,r3
- +8c: 7c 74 01 20 mtocrf 64,r3
- +90: 7c 78 01 20 mtocrf 128,r3
- +94: 7c 60 00 26 mfcr r3
- +98: 7c 70 10 26 mfocrf r3,1
- +9c: 7c 70 20 26 mfocrf r3,2
- +a0: 7c 70 40 26 mfocrf r3,4
- +a4: 7c 70 80 26 mfocrf r3,8
- +a8: 7c 71 00 26 mfocrf r3,16
- +ac: 7c 72 00 26 mfocrf r3,32
- +b0: 7c 74 00 26 mfocrf r3,64
- +b4: 7c 78 00 26 mfocrf r3,128
- +b8: 7c 01 17 ec dcbz r1,r2
- +bc: 7c 23 27 ec dcbzl r3,r4
- +c0: 7c 05 37 ec dcbz r5,r6
- +c4: e0 40 00 10 lq r2,16\(0\)
- +c8: e0 05 00 10 lq r0,16\(r5\)
- +cc: e0 45 00 10 lq r2,16\(r5\)
- +d0: f8 40 00 12 stq r2,16\(0\)
- +d4: f8 05 00 12 stq r0,16\(r5\)
- +d8: f8 45 00 12 stq r2,16\(r5\)
+.*: e0 83 00 00 lq r4,0\(r3\)
+.*: R_PPC64_ADDR16_LO_DS \.data
+.*: e0 83 00 10 lq r4,16\(r3\)
+.*: R_PPC64_ADDR16_LO_DS \.data\+0x10
+.*: e0 83 00 10 lq r4,16\(r3\)
+.*: R_PPC64_ADDR16_LO_DS \.data\+0x10
+.*: e0 83 00 20 lq r4,32\(r3\)
+.*: R_PPC64_ADDR16_LO_DS \.data\+0x20
+.*: e0 83 00 00 lq r4,0\(r3\)
+.*: R_PPC64_ADDR16_LO_DS esym0
+.*: e0 83 00 00 lq r4,0\(r3\)
+.*: R_PPC64_ADDR16_LO_DS esym1
+.*: e0 82 00 00 lq r4,0\(r2\)
+.*: R_PPC64_TOC16_DS \.toc
+.*: e0 82 00 10 lq r4,16\(r2\)
+.*: R_PPC64_TOC16_DS \.toc\+0x10
+.*: e0 80 00 00 lq r4,0\(0\)
+.*: R_PPC64_ADDR16_LO_DS \.text
+.*: e0 c3 00 00 lq r6,0\(r3\)
+.*: R_PPC64_GOT16_DS dsym0
+.*: e0 c3 00 00 lq r6,0\(r3\)
+.*: R_PPC64_GOT16_LO_DS dsym0
+.*: e0 c3 00 00 lq r6,0\(r3\)
+.*: R_PPC64_PLT16_LO_DS \.data
+.*: e0 c3 00 10 lq r6,16\(r3\)
+.*: R_PPC64_SECTOFF_DS \.data\+0x10
+.*: e0 c3 00 10 lq r6,16\(r3\)
+.*: R_PPC64_SECTOFF_LO_DS \.data\+0x10
+.*: e0 c4 00 20 lq r6,32\(r4\)
+.*: f8 c7 00 02 stq r6,0\(r7\)
+.*: f8 c7 00 12 stq r6,16\(r7\)
+.*: f8 c7 ff f2 stq r6,-16\(r7\)
+.*: f8 c7 80 02 stq r6,-32768\(r7\)
+.*: f8 c7 7f f2 stq r6,32752\(r7\)
+.*: 00 00 02 00 attn
+.*: 7c 6f f1 20 mtcr r3
+.*: 7c 6f f1 20 mtcr r3
+.*: 7c 68 11 20 mtcrf 129,r3
+.*: 7c 70 11 20 mtocrf 1,r3
+.*: 7c 70 21 20 mtocrf 2,r3
+.*: 7c 70 41 20 mtocrf 4,r3
+.*: 7c 70 81 20 mtocrf 8,r3
+.*: 7c 71 01 20 mtocrf 16,r3
+.*: 7c 72 01 20 mtocrf 32,r3
+.*: 7c 74 01 20 mtocrf 64,r3
+.*: 7c 78 01 20 mtocrf 128,r3
+.*: 7c 60 00 26 mfcr r3
+.*: 7c 70 10 26 mfocrf r3,1
+.*: 7c 70 20 26 mfocrf r3,2
+.*: 7c 70 40 26 mfocrf r3,4
+.*: 7c 70 80 26 mfocrf r3,8
+.*: 7c 71 00 26 mfocrf r3,16
+.*: 7c 72 00 26 mfocrf r3,32
+.*: 7c 74 00 26 mfocrf r3,64
+.*: 7c 78 00 26 mfocrf r3,128
+.*: 7c 01 17 ec dcbz r1,r2
+.*: 7c 23 27 ec dcbzl r3,r4
+.*: 7c 05 37 ec dcbz r5,r6
+.*: e0 40 00 10 lq r2,16\(0\)
+.*: e0 05 00 10 lq r0,16\(r5\)
+.*: e0 45 00 10 lq r2,16\(r5\)
+.*: f8 40 00 12 stq r2,16\(0\)
+.*: f8 05 00 12 stq r0,16\(r5\)
+.*: f8 45 00 12 stq r2,16\(r5\)
Index: gas/testsuite/gas/ppc/power4.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/power4.s,v
retrieving revision 1.3
diff -u -p -r1.3 power4.s
--- gas/testsuite/gas/ppc/power4.s 15 Aug 2012 21:25:21 -0000 1.3
+++ gas/testsuite/gas/ppc/power4.s 25 Oct 2012 23:54:53 -0000
@@ -1,22 +1,20 @@
.section ".data"
+ .p2align 4
dsym0: .llong 0xdeadbeef
+ .llong 0xc0ffee
dsym1:
.section ".toc"
+ .p2align 4
.L_tsym0:
.tc ignored0[TC],dsym0
-.L_tsym1:
.tc ignored1[TC],dsym1
-.L_tsym2:
+.L_tsym1:
.tc ignored2[TC],usym0
-.L_tsym3:
.tc ignored3[TC],usym1
-.L_tsym4:
- .tc ignored4[TC],esym0
-.L_tsym5:
- .tc ignored5[TC],esym1
.section ".text"
+ .p2align 4
lq 4,dsym0@l(3)
lq 4,dsym1@l(3)
lq 4,usym0@l(3)
@@ -25,11 +23,6 @@ dsym1:
lq 4,esym1@l(3)
lq 4,.L_tsym0@toc(2)
lq 4,.L_tsym1@toc(2)
- lq 4,.L_tsym2@toc(2)
- lq 4,.L_tsym3@toc(2)
- lq 4,.L_tsym4@toc(2)
- lq 4,.L_tsym5@toc(2)
- lq 6,.L_tsym5@toc@l(2)
lq 4,.text@l(0)
lq 6,dsym0@got(3)
lq 6,dsym0@got@l(3)
@@ -81,5 +74,6 @@ dsym1:
.section ".data"
usym0: .llong 0xcafebabe
+ .llong 0xc0ffee
usym1:
--
Alan Modra
Australia Development Lab, IBM