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[Patch, microblaze, gas, opcodes] Add support for clz insn


Add opcode for count leading zeros (clz) instruction,
counts number of leading zeros in register rA starting
from msb.

Expand microblaze allinsn.{s,d} testsuite coverage to
include new instruction.


binutils/opcodes/Changelog

 2012-11-08  Edgar E. Iglesias <edgar.iglesias@gmail.com>

          * microblaze-opc.h: Increase MAX_OPCODES
            (op_code_struct):  add clz insn
          * microblaze-opcm.h (microblaze_instr): add clz

binutils/gas/testsuite/Changelog

 2012-11-08  David Holsgrove  <david.holsgrove@xilinx.com>

          * gas/microblaze/allinsn.s: Add clz insn
          * gas/microblaze/allinsn.d: Likewise

From 48fc6c21ec178ce70a7472bfcd763da83080b7ad Mon Sep 17 00:00:00 2001
From: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Date: Wed, 2 Nov 2011 21:57:07 +0100
Subject: [PATCH] opcodes/ * microblaze-opc.h: Add support for clz insn

Add opcode for count leading zeros (clz) instruction,
counts number of leading zeros in register rA starting
from msb.

Add clz to microblaze allinsn testsuite coverage

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
---
 gas/testsuite/gas/microblaze/allinsn.d |    3 +++
 gas/testsuite/gas/microblaze/allinsn.s |    4 ++++
 opcodes/microblaze-opc.h               |    3 ++-
 opcodes/microblaze-opcm.h              |    2 +-
 4 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/gas/testsuite/gas/microblaze/allinsn.d b/gas/testsuite/gas/microblaze/allinsn.d
index 79064ba..c7854f1 100644
--- a/gas/testsuite/gas/microblaze/allinsn.d
+++ b/gas/testsuite/gas/microblaze/allinsn.d
@@ -22,3 +22,6 @@ Disassembly of section .text:
 
 00000014 <swr>:
   14:	d8000200 	swr	r0, r0, r0
+
+00000018 <clz>:
+  18:	900000e0 	clz	r0, r0
diff --git a/gas/testsuite/gas/microblaze/allinsn.s b/gas/testsuite/gas/microblaze/allinsn.s
index 8bb3ef5..0e4271d 100644
--- a/gas/testsuite/gas/microblaze/allinsn.s
+++ b/gas/testsuite/gas/microblaze/allinsn.s
@@ -24,4 +24,8 @@ shr:
     .global swr
 swr:
     swr r0,r0,r0
+    .text
+    .global clz
+clz:
+    clz r0,r0
 
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 44c9d38..132b951 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -96,7 +96,7 @@
 #define DELAY_SLOT 1
 #define NO_DELAY_SLOT 0
 
-#define MAX_OPCODES 284
+#define MAX_OPCODES 285
 
 struct op_code_struct
 {
@@ -394,6 +394,7 @@ struct op_code_struct
   {"tneaputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd,  anyware_inst },
   {"necaputd",  INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd,  anyware_inst },
   {"tnecaputd", INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
+  {"clz",       INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34,  clz,       special_inst },
   {"", 0, 0, 0, 0, 0, 0, 0, 0},
 };
 
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 522d9a8..661d836 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -25,7 +25,7 @@
 
 enum microblaze_instr
 {
-  add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu,
+  add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, 
   mulh, mulhu, mulhsu,
   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
-- 
1.7.0.4


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