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Commit: V850: Fix encoding of PREPARE insn


Hi Guys,

  I am checking in the patch below to fix the encoding of the V850's
  PREPARE instruction, which can take a negative value for the stack
  increment.  The patch also fixes up a problem in the gas testsuite
  where the new V850 reloc names were not being handled.

  Tested without regressions on a v850e-elf toolchain.

Cheers
  Nick

gas/ChangeLog
2013-01-15  Nick Clifton  <nickc@redhat.com>

	* config/tc-v850.c (md_assemble): Allow signed values for
	V850E_IMMEDIATE.

gas/testsuite/ChangeLog
2013-01-15  Nick Clifton  <nickc@redhat.com>

	* gas/v850/basic.exp: Allow for variations in reloc names.
	* gas/v850/split-lo16.d: Likewise.

	* gas/v850/v850e1.s: Add more tests of the PREPARE insn.
	* gas/v850/v850e1.d: Update expected disassembly.

opcodes/ChangeLog
2013-01-15  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
	values.
	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.

Index: gas/config/tc-v850.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-v850.c,v
retrieving revision 1.61
diff -u -3 -p -r1.61 tc-v850.c
--- gas/config/tc-v850.c	9 Nov 2012 17:36:14 -0000	1.61
+++ gas/config/tc-v850.c	15 Jan 2013 08:36:24 -0000
@@ -2350,7 +2350,8 @@ md_assemble (char *str)
 		    }
 		  if (operand->flags & V850E_IMMEDIATE16)
 		    {
-		      if (ex.X_add_number & 0xffff0000)
+		      if ((ex.X_add_number & 0xffff0000)
+			  && ((ex.X_add_number & 0xffff0000) != 0xffff0000))
 			{
 			  errmsg = _("constant too big to fit into instruction");
 			  goto error;
Index: gas/testsuite/gas/v850/basic.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/v850/basic.exp,v
retrieving revision 1.9
diff -u -3 -p -r1.9 basic.exp
--- gas/testsuite/gas/v850/basic.exp	14 Jan 2013 13:11:31 -0000	1.9
+++ gas/testsuite/gas/v850/basic.exp	15 Jan 2013 08:36:25 -0000
@@ -386,17 +386,17 @@ proc do_simple_reloc_tests {} {
 
 	while 1 {
 	    expect {
-		-re "^00000002\[^\n\]*R_V850_LO16\[^\n\]*\n"
+		-re "^00000002\[^\n\]*R_V8\[A-Z0-9_\]+\[^\n\]*\n"
 			{ set x [expr $x+1] }
-		-re "^00000006\[^\n\]*R_V850_HI16_S\[^\n\]*\n"
+		-re "^00000006\[^\n\]*R_V8\[A-Z0-9_\]+\[^\n\]*\n"
 			{ set x [expr $x+1] }
-		-re "^0000000a\[^\n\]*R_V850_HI16\[^\n\]*\n"
+		-re "^0000000a\[^\n\]*R_V8\[A-Z0-9_\]+\[^\n\]*\n"
 			{ set x [expr $x+1] }
-		-re "^0000000e\[^\n\]*R_V850_ZDA_16_16_OFFSET\[^\n\]*\n"
+		-re "^0000000e\[^\n\]*R_V8\[A-Z0-9_\]+\[^\n\]*\n"
 			{ set x [expr $x+1] }
-		-re "^00000012\[^\n\]*R_V850_TDA_16_16_OFFSET\[^\n\]*\n"
+		-re "^00000012\[^\n\]*R_V8\[A-Z0-9_\]+\[^\n\]*\n"
 			{ set x [expr $x+1] }
-		-re "^00000016\[^\n\]*R_V850_SDA_16_16_OFFSET\[^\n\]*\n"
+		-re "^00000016\[^\n\]*R_V8\[A-Z0-9_\]+\[^\n\]*\n"
 			{ set x [expr $x+1] }
 		-re "\[^\n\]*\n"				{ }
 		timeout			{ perror "timeout\n"; break }
Index: gas/testsuite/gas/v850/split-lo16.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/v850/split-lo16.d,v
retrieving revision 1.4
diff -u -3 -p -r1.4 split-lo16.d
--- gas/testsuite/gas/v850/split-lo16.d	14 Jan 2013 13:11:31 -0000	1.4
+++ gas/testsuite/gas/v850/split-lo16.d	15 Jan 2013 08:36:25 -0000
@@ -4,13 +4,13 @@
 #...
 00000000 <.*>:
    0:	40 0e 00 00 	movhi	0, r0, r1
-			2: R_V850_HI16_S	foo
+			2: R_V8.*	foo
    4:	01 16 00 00 	addi	0, r1, r2
-			6: R_V850_LO16	foo
+			6: R_V8.*	foo
    8:	01 17 00 00 	ld\.b	0\[r1\], r2
-			a: R_V850_LO16	foo
+			a: R_V8.*	foo
    c:	81 17 01 00 	ld\.bu	0\[r1\], r2
-			c: R_V850_LO16_SPLIT_OFFSET	foo
+			c: R_V8.*	foo
   10:	a1 17 45 23 	ld\.bu	9029\[r1\], r2
   14:	81 17 57 34 	ld\.bu	13398\[r1\], r2
   18:	20 57 01 00 	ld.w	0\[r0\], r10
Index: gas/testsuite/gas/v850/v850e1.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/v850/v850e1.d,v
retrieving revision 1.6
diff -u -3 -p -r1.6 v850e1.d
--- gas/testsuite/gas/v850/v850e1.d	4 Oct 2012 10:30:05 -0000	1.6
+++ gas/testsuite/gas/v850/v850e1.d	15 Jan 2013 08:36:25 -0000
@@ -43,3 +43,4 @@ Disassembly of section .text:
 0x0+7a 83 00  [ 	]*zxb	sp
 0x0+7c c4 00  [ 	]*zxh	gp
 0x0+7e 63 ff 9d 00[ 	]*st.w	lp, 156\[sp\]
+0x0+82 80 07 0b e8 f6 ff[ 	]*prepare	{r20, r24 - r26}, 0, -10
Index: gas/testsuite/gas/v850/v850e1.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/v850/v850e1.s,v
retrieving revision 1.2
diff -u -3 -p -r1.2 v850e1.s
--- gas/testsuite/gas/v850/v850e1.s	13 Apr 2011 13:20:24 -0000	1.2
+++ gas/testsuite/gas/v850/v850e1.s	15 Jan 2013 08:36:25 -0000
@@ -37,3 +37,4 @@
 	zxb	r3
 	zxh	r4
 	st.w    lp, 156[sp]
+	prepare {r20,r24,r25,r26},0,-10
Index: opcodes/v850-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/v850-dis.c,v
retrieving revision 1.16
diff -u -3 -p -r1.16 v850-dis.c
--- opcodes/v850-dis.c	4 Oct 2012 10:30:06 -0000	1.16
+++ opcodes/v850-dis.c	15 Jan 2013 08:36:25 -0000
@@ -118,6 +118,8 @@ get_operand_value (const struct v850_ope
 
 	  if (operand->flags & V850E_IMMEDIATE16HI)
 	    value <<= 16;
+	  else if (value & 0x8000)
+	    value |= (-1L << 16);
 
 	  return value;
 	}
Index: opcodes/v850-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/v850-opc.c,v
retrieving revision 1.15
diff -u -3 -p -r1.15 v850-opc.c
--- opcodes/v850-opc.c	17 May 2012 15:13:26 -0000	1.15
+++ opcodes/v850-opc.c	15 Jan 2013 08:36:25 -0000
@@ -747,9 +747,9 @@ const struct v850_operand v850_operands[
 #define IMM16	(I16 + 1)
   { 16, 32, NULL, NULL, V850E_IMMEDIATE16, BFD_RELOC_16 },
 
-/* The 16 bit immediate following a 32 bit instruction.  */
+/* The signed 16 bit immediate following a prepare instruction.  */
 #define IMM16LO	(IMM16 + 1)
-  { 16, 32, NULL, NULL, V850E_IMMEDIATE16, BFD_RELOC_LO16 },
+  { 16, 32, NULL, NULL, V850E_IMMEDIATE16 | V850_OPERAND_SIGNED, BFD_RELOC_LO16 },
 
 /* The hi 16 bit immediate following a 32 bit instruction.  */
 #define IMM16HI	(IMM16LO + 1)


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