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[Patch, AArch64] Add support for alias instructions SXTL, SXTL2, UXTL and UXTL2
- From: Yufeng Zhang <Yufeng dot Zhang at arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>
- Date: Tue, 29 Jan 2013 18:42:16 +0000
- Subject: [Patch, AArch64] Add support for alias instructions SXTL, SXTL2, UXTL and UXTL2
Hi,
This patch adds support in GAS and opcodes for SXTL, SXTL2, UXTL and
UXTL2 as the preferred aliases for SSHLL, SSHLL2, USHLL and USHLL2 with
an immediate shift of #0.
OK for the trunk and the 2.23 branch?
Thanks,
Yufeng
include/opcode/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
opcodes/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
* aarch64-asm.c (convert_xtl_to_shll): New function.
(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_xtl_to_shll.
* aarch64-dis.c (convert_shll_to_xtl): New function.
(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_shll_to_xtl.
* aarch64-asm-2.c: Re-generate.
* aarch64-dis-2.c: Re-generate.
* aarch64-opc-2.c: Re-generate.
gas/testsuite/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/alias.s: Add new tests.
* gas/aarch64/alias.d: Update.
* gas/aarch64/no-aliases.d: Update.
diff --git a/gas/testsuite/gas/aarch64/alias.d b/gas/testsuite/gas/aarch64/alias.d
index ddc2157..53cf5e9 100644
--- a/gas/testsuite/gas/aarch64/alias.d
+++ b/gas/testsuite/gas/aarch64/alias.d
@@ -72,3 +72,27 @@ Disassembly of section \.text:
100: b13ffdff cmn x15, #0xfff
104: f13fffef subs x15, sp, #0xfff
108: b13ffdff cmn x15, #0xfff
+ 10c: 0f08a448 sxtl v8.8h, v2.8b
+ 110: 0f08a448 sxtl v8.8h, v2.8b
+ 114: 4f08a448 sxtl2 v8.8h, v2.16b
+ 118: 4f08a448 sxtl2 v8.8h, v2.16b
+ 11c: 0f10a448 sxtl v8.4s, v2.4h
+ 120: 0f10a448 sxtl v8.4s, v2.4h
+ 124: 4f10a448 sxtl2 v8.4s, v2.8h
+ 128: 4f10a448 sxtl2 v8.4s, v2.8h
+ 12c: 0f20a448 sxtl v8.2d, v2.2s
+ 130: 0f20a448 sxtl v8.2d, v2.2s
+ 134: 4f20a448 sxtl2 v8.2d, v2.4s
+ 138: 4f20a448 sxtl2 v8.2d, v2.4s
+ 13c: 2f08a448 uxtl v8.8h, v2.8b
+ 140: 2f08a448 uxtl v8.8h, v2.8b
+ 144: 6f08a448 uxtl2 v8.8h, v2.16b
+ 148: 6f08a448 uxtl2 v8.8h, v2.16b
+ 14c: 2f10a448 uxtl v8.4s, v2.4h
+ 150: 2f10a448 uxtl v8.4s, v2.4h
+ 154: 6f10a448 uxtl2 v8.4s, v2.8h
+ 158: 6f10a448 uxtl2 v8.4s, v2.8h
+ 15c: 2f20a448 uxtl v8.2d, v2.2s
+ 160: 2f20a448 uxtl v8.2d, v2.2s
+ 164: 6f20a448 uxtl2 v8.2d, v2.4s
+ 168: 6f20a448 uxtl2 v8.2d, v2.4s
diff --git a/gas/testsuite/gas/aarch64/alias.s b/gas/testsuite/gas/aarch64/alias.s
index c2b71b9..0db9aff 100644
--- a/gas/testsuite/gas/aarch64/alias.s
+++ b/gas/testsuite/gas/aarch64/alias.s
@@ -2,7 +2,7 @@
preference. It is also used to test the -Mno-aliases option in
the disassemler.
- Copyright 2012 Free Software Foundation, Inc.
+ Copyright 2012, 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
@@ -99,3 +99,21 @@
adds xzr, x15, #0xfff
subs x15, sp, #0xfff
cmn x15, #0xfff
+
+ .macro asimdshll s
+ \s\()xtl v8.8h, v2.8b
+ \s\()shll v8.8h, v2.8b, #0
+ \s\()xtl2 v8.8h, v2.16b
+ \s\()shll2 v8.8h, v2.16b, #0
+ \s\()xtl v8.4s, v2.4h
+ \s\()shll v8.4s, v2.4h, #0
+ \s\()xtl2 v8.4s, v2.8h
+ \s\()shll2 v8.4s, v2.8h, #0
+ \s\()xtl v8.2d, v2.2s
+ \s\()shll v8.2d, v2.2s, #0
+ \s\()xtl2 v8.2d, v2.4s
+ \s\()shll2 v8.2d, v2.4s, #0
+ .endm
+
+ asimdshll s
+ asimdshll u
diff --git a/gas/testsuite/gas/aarch64/no-aliases.d b/gas/testsuite/gas/aarch64/no-aliases.d
index 5ccf80b..1065094 100644
--- a/gas/testsuite/gas/aarch64/no-aliases.d
+++ b/gas/testsuite/gas/aarch64/no-aliases.d
@@ -73,3 +73,27 @@ Disassembly of section \.text:
100: b13ffdff adds xzr, x15, #0xfff
104: f13fffef subs x15, sp, #0xfff
108: b13ffdff adds xzr, x15, #0xfff
+ 10c: 0f08a448 sshll v8.8h, v2.8b, #0
+ 110: 0f08a448 sshll v8.8h, v2.8b, #0
+ 114: 4f08a448 sshll2 v8.8h, v2.16b, #0
+ 118: 4f08a448 sshll2 v8.8h, v2.16b, #0
+ 11c: 0f10a448 sshll v8.4s, v2.4h, #0
+ 120: 0f10a448 sshll v8.4s, v2.4h, #0
+ 124: 4f10a448 sshll2 v8.4s, v2.8h, #0
+ 128: 4f10a448 sshll2 v8.4s, v2.8h, #0
+ 12c: 0f20a448 sshll v8.2d, v2.2s, #0
+ 130: 0f20a448 sshll v8.2d, v2.2s, #0
+ 134: 4f20a448 sshll2 v8.2d, v2.4s, #0
+ 138: 4f20a448 sshll2 v8.2d, v2.4s, #0
+ 13c: 2f08a448 ushll v8.8h, v2.8b, #0
+ 140: 2f08a448 ushll v8.8h, v2.8b, #0
+ 144: 6f08a448 ushll2 v8.8h, v2.16b, #0
+ 148: 6f08a448 ushll2 v8.8h, v2.16b, #0
+ 14c: 2f10a448 ushll v8.4s, v2.4h, #0
+ 150: 2f10a448 ushll v8.4s, v2.4h, #0
+ 154: 6f10a448 ushll2 v8.4s, v2.8h, #0
+ 158: 6f10a448 ushll2 v8.4s, v2.8h, #0
+ 15c: 2f20a448 ushll v8.2d, v2.2s, #0
+ 160: 2f20a448 ushll v8.2d, v2.2s, #0
+ 164: 6f20a448 ushll2 v8.2d, v2.4s, #0
+ 168: 6f20a448 ushll2 v8.2d, v2.4s, #0
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9005c8c..ec5aca7 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -424,6 +424,11 @@ enum aarch64_op
OP_ROR_IMM,
+ OP_SXTL,
+ OP_SXTL2,
+ OP_UXTL,
+ OP_UXTL2,
+
OP_TOTAL_NUM, /* Pseudo. */
};
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 4c1c521..ad3cdf0 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -958,6 +958,16 @@ convert_ror_to_extr (aarch64_inst *inst)
copy_operand_info (inst, 2, 1);
}
+/* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
+ is equivalent to:
+ USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
+static void
+convert_xtl_to_shll (aarch64_inst *inst)
+{
+ inst->operands[2].qualifier = inst->operands[1].qualifier;
+ inst->operands[2].imm.value = 0;
+}
+
/* Convert
LSR <Xd>, <Xn>, #<shift>
to
@@ -1167,6 +1177,12 @@ convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
case OP_ROR_IMM:
convert_ror_to_extr (inst);
break;
+ case OP_SXTL:
+ case OP_SXTL2:
+ case OP_UXTL:
+ case OP_UXTL2:
+ convert_xtl_to_shll (inst);
+ break;
default:
break;
}
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index bbd5a3e..90ab5b2 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1478,6 +1478,20 @@ convert_extr_to_ror (aarch64_inst *inst)
return 0;
}
+/* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
+ is equivalent to:
+ USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
+static int
+convert_shll_to_xtl (aarch64_inst *inst)
+{
+ if (inst->operands[2].imm.value == 0)
+ {
+ inst->operands[2].type = AARCH64_OPND_NIL;
+ return 1;
+ }
+ return 0;
+}
+
/* Convert
UBFM <Xd>, <Xn>, #<shift>, #63.
to
@@ -1731,6 +1745,11 @@ convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
return convert_movebitmask_to_mov (inst);
case OP_ROR_IMM:
return convert_extr_to_ror (inst);
+ case OP_SXTL:
+ case OP_SXTL2:
+ case OP_UXTL:
+ case OP_UXTL2:
+ return convert_shll_to_xtl (inst);
default:
return 0;
}
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index e2906f8..678ba78 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1534,8 +1534,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
{"sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
{"sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
- {"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, 0},
- {"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, 0},
+ {"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
+ {"sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
+ {"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
+ {"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
{"scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
{"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
{"ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
@@ -1554,8 +1556,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
{"uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
{"uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
- {"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, 0},
- {"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, 0},
+ {"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
+ {"uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
+ {"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
+ {"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
{"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
{"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
/* AdvSIMD TBL/TBX. */