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[PATCH][AARCH64] Allow the TLS GD sequence to be split

From: "Sofiane Naci" <sofiane dot naci at arm dot com>
To: <binutils at sourceware dot org>
Date: Thu, 21 Feb 2013 12:47:39 -0000
Subject: [PATCH][AARCH64] Allow the TLS GD sequence to be split

Hi,

The AArch64 BFD linker currently expects that the TLS GD instructions are
sequential:

   add     x0, x0, #0x0     R_AARCH64_TLSGD_ADD_LO12_NC
   bl      __tls_get_addr   R_AARCH64_CALL26
   nop

Given that we have different relocs on the ADD and the BL, we can improve
relaxation to work on the two instructions even when they are not
sequential. This will allow the compiler to break the sequence above if
better scheduling can be achieved.

I've also added new LD tests to check relaxations happen as expected when
the instructions above are not sequential.

Thanks
Sofiane

Attachment: aarch64-split-bdf-relax.patch
Description: Binary data

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