This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
PATCH: Add RegRex64 to riz
- From: "H.J. Lu" <hongjiu dot lu at intel dot com>
- To: binutils at sourceware dot org
- Date: Fri, 1 Mar 2013 17:58:22 -0800
- Subject: PATCH: Add RegRex64 to riz
- Reply-to: "H.J. Lu" <hjl dot tools at gmail dot com>
Hi,
I checked in this patch to add RegRex64 to riz.
H.J.
---
Index: ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.1942
diff -u -p -r1.1942 ChangeLog
--- ChangeLog 28 Feb 2013 19:18:40 -0000 1.1942
+++ ChangeLog 2 Mar 2013 01:57:20 -0000
@@ -1,3 +1,8 @@
+2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-reg.tbl (riz): Add RegRex64.
+ * i386-tbl.h: Regenerated.
+
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
Index: i386-reg.tbl
===================================================================
RCS file: /cvs/src/src/opcodes/i386-reg.tbl,v
retrieving revision 1.12
diff -u -p -r1.12 i386-reg.tbl
--- i386-reg.tbl 2 Sep 2009 07:20:29 -0000 1.12
+++ i386-reg.tbl 2 Mar 2013 01:57:20 -0000
@@ -211,8 +211,8 @@ rip, BaseIndex, RegRex64, RegRip, Dw2Inv
eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
// No type will make these registers rejected for all purposes except
// for addressing.
+riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
-riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval
// fp regs.
st(0), FloatReg|FloatAcc, 0, 0, 11, 33
st(1), FloatReg, 0, 1, 12, 34
Index: i386-tbl.h
===================================================================
RCS file: /cvs/src/src/opcodes/i386-tbl.h,v
retrieving revision 1.115
diff -u -p -r1.115 i386-tbl.h
--- i386-tbl.h 19 Feb 2013 19:10:31 -0000 1.115
+++ i386-tbl.h 2 Mar 2013 01:57:24 -0000
@@ -40246,16 +40246,16 @@ const reg_entry i386_regtab[] =
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
RegRex64, RegEip, { 8, Dw2Inval } },
- { "eiz",
+ { "riz",
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- 0, RegEiz, { Dw2Inval, Dw2Inval } },
- { "riz",
+ RegRex64, RegRiz, { Dw2Inval, Dw2Inval } },
+ { "eiz",
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- 0, RegRiz, { Dw2Inval, Dw2Inval } },
+ 0, RegEiz, { Dw2Inval, Dw2Inval } },
{ "st(0)",
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,