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Commit: V850: Add FPU-3.0 multiply-add insns.
- From: Nick Clifton <nickc at redhat dot com>
- To: binutils at sourceware dot org
- Date: Wed, 03 Apr 2013 15:36:21 +0100
- Subject: Commit: V850: Add FPU-3.0 multiply-add insns.
Hi Guys,
I am applying the patch below to add support for the FPU-3.0
multiply-add instructions used by the E3V5 version of the V850
architecture.
The patch also includes a fix for the E3V5 LOOP instruction which
takes a positive value to indicate a negative displacement.
Finally V850 local symbols are now also treated as special symbols,
which helps GDB when it is attempting to find the name of a function.
Tested with a v850-elf toolchain with no regressions.
Cheers
Nick
bfd/ChangeLog
2013-04-03 Nick Clifton <nickc@redhat.com>
* elf32-v850.c (v850_elf_is_target_special_symbol): New function.
(bfd_elf32_bfd_is_target_special_symbol): Define.
include/opcode/ChangeLog
2013-04-03 Nick Clifton <nickc@redhat.com>
* v850.h (V850_INVERSE_PCREL): Define.
opcodes/ChangeLog
2013-04-03 Nick Clifton <nickc@redhat.com>
* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
destination address by subtracting the operand from the current
address.
* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
a positive value in the insn.
(extract_u16_loop): Do not negate the returned value.
(D16_LOOP): Add V850_INVERSE_PCREL flag.
(ceilf.sw): Remove duplicate entry.
(cvtf.hs): New entry.
(cvtf.sh): Likewise.
(fmaf.s): Likewise.
(fmsf.s): Likewise.
(fnmaf.s): Likewise.
(fnmsf.s): Likewise.
(maddf.s): Restrict to E3V5 architectures.
(msubf.s): Likewise.
(nmaddf.s): Likewise.
(nmsubf.s): Likewise.
Index: bfd/elf32-v850.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-v850.c,v
retrieving revision 1.88
diff -u -3 -p -r1.88 elf32-v850.c
--- bfd/elf32-v850.c 30 Mar 2013 10:14:15 -0000 1.88
+++ bfd/elf32-v850.c 3 Apr 2013 14:23:19 -0000
@@ -1920,6 +1920,12 @@ v850_elf_is_local_label_name (bfd *abfd
return ( (name[0] == '.' && (name[1] == 'L' || name[1] == '.'))
|| (name[0] == '_' && name[1] == '.' && name[2] == 'L' && name[3] == '_'));
}
+
+static bfd_boolean
+v850_elf_is_target_special_symbol (bfd *abfd, asymbol *sym)
+{
+ return v850_elf_is_local_label_name (abfd, sym->name);
+}
/* We overload some of the bfd_reloc error codes for own purposes. */
#define bfd_reloc_gp_not_found bfd_reloc_other
@@ -3791,6 +3797,8 @@ static const struct bfd_elf_special_sect
#define elf_backend_rela_normal 1
#define bfd_elf32_bfd_is_local_label_name v850_elf_is_local_label_name
+#define bfd_elf32_bfd_is_target_special_symbol v850_elf_is_target_special_symbol
+
#define bfd_elf32_bfd_reloc_type_lookup v850_elf_reloc_type_lookup
#define bfd_elf32_bfd_reloc_name_lookup v850_elf_reloc_name_lookup
#define bfd_elf32_bfd_merge_private_bfd_data v850_elf_merge_private_bfd_data
Index: include/opcode/v850.h
===================================================================
RCS file: /cvs/src/src/include/opcode/v850.h,v
retrieving revision 1.9
diff -u -3 -p -r1.9 v850.h
--- include/opcode/v850.h 24 Jan 2013 16:51:56 -0000 1.9
+++ include/opcode/v850.h 3 Apr 2013 14:23:19 -0000
@@ -232,6 +232,9 @@ extern const struct v850_operand v850_op
/* This operand is a prefetch oparation. */
#define V850_OPERAND_PREFOP 0x800000
+/* A PC-relative displacement where a positive value indicates a backwards displacement. */
+#define V850_INVERSE_PCREL 0x1000000
+
extern int v850_msg_is_out_of_range (const char *);
#endif /* V850_H */
Index: opcodes/v850-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/v850-dis.c,v
retrieving revision 1.18
diff -u -3 -p -r1.18 v850-dis.c
--- opcodes/v850-dis.c 24 Jan 2013 11:14:05 -0000 1.18
+++ opcodes/v850-dis.c 3 Apr 2013 14:23:19 -0000
@@ -94,6 +94,8 @@ print_value (int flags,
if (flags & V850_PCREL)
{
bfd_vma addr = value + memaddr;
+ if (flags & V850_INVERSE_PCREL)
+ addr = memaddr - value;
info->print_address_func (addr, info);
}
else if (flags & V850_OPERAND_DISP)
Index: opcodes/v850-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/v850-opc.c,v
retrieving revision 1.17
diff -u -3 -p -r1.17 v850-opc.c
--- opcodes/v850-opc.c 24 Jan 2013 11:14:05 -0000 1.17
+++ opcodes/v850-opc.c 3 Apr 2013 14:23:19 -0000
@@ -301,7 +301,9 @@ extract_d9 (unsigned long insn, int * in
static unsigned long
insert_u16_loop (unsigned long insn, long value, const char ** errmsg)
{
- if (value < -0xffff || value > 0)
+ /* Loop displacement is encoded as a positive value,
+ even though the instruction branches backwards. */
+ if (value < 0 || value > 0xffff)
{
if ((value % 2) != 0)
* errmsg = branch_out_of_range_and_odd_offset;
@@ -311,14 +313,13 @@ insert_u16_loop (unsigned long insn, lon
else if ((value % 2) != 0)
* errmsg = branch_to_odd_offset;
- return insn | ((-value & 0xfffe) << 16);
+ return insn | ((value & 0xfffe) << 16);
}
static unsigned long
extract_u16_loop (unsigned long insn, int * invalid)
{
long ret = (insn >> 16) & 0xfffe;
- ret = -ret;
if (invalid != 0)
*invalid = 0;
@@ -1211,7 +1212,7 @@ const struct v850_operand v850_operands[
/* The unsigned DISP16 field in a format 7 insn. */
#define D16_LOOP (D16_15 + 1)
- { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_16_PCREL },
+ { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL | V850_INVERSE_PCREL, BFD_RELOC_V850_16_PCREL },
/* The DISP17 field in a format 7 insn. */
#define D17_16 (D16_LOOP + 1)
@@ -1814,7 +1815,6 @@ const struct v850_opcode v850_opcodes[]
{ "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
{ "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
{ "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
-{ "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
{ "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
/* Default value for FFF is 0(not defined in spec). */
{ "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
@@ -1830,10 +1830,12 @@ const struct v850_opcode v850_opcodes[]
{ "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
{ "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
{ "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.hs", two (0x07e2, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP },
{ "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
{ "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
{ "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
{ "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
+{ "cvtf.sh", two (0x07e3, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP },
{ "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
{ "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
{ "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
@@ -1853,18 +1855,22 @@ const struct v850_opcode v850_opcodes[]
{ "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
{ "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
{ "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
-{ "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP },
+{ "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
+{ "fmaf.s", two (0x07e0, 0x04e0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
{ "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
{ "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
{ "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
{ "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
-{ "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP },
+{ "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
+{ "fmsf.s", two (0x07e0, 0x04e2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
{ "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
{ "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
{ "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
{ "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
-{ "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP },
-{ "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP },
+{ "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
+{ "fnmaf.s", two (0x07e0, 0x04e4), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
+{ "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
+{ "fnmsf.s", two (0x07e0, 0x04e6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
{ "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
{ "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },