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Re: [PATCH] Add MIPS ufr macro instruction
- From: "Maciej W. Rozycki" <macro at codesourcery dot com>
- To: Richard Sandiford <rdsandiford at googlemail dot com>
- Cc: Andrew Bennett <Andrew dot Bennett at imgtec dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Fri, 13 Dec 2013 18:36:37 +0000
- Subject: Re: [PATCH] Add MIPS ufr macro instruction
- Authentication-results: sourceware.org; auth=none
- References: <0DA23CC379F5F945ACB41CF394B982774C835E at LEMAIL01 dot le dot imgtec dot org> <87vc01erxi dot fsf at talisman dot default> <87siuzcpp4 dot fsf at talisman dot default> <0DA23CC379F5F945ACB41CF394B982774CB15B at LEMAIL01 dot le dot imgtec dot org> <0DA23CC379F5F945ACB41CF394B982774CE268 at LEMAIL01 dot le dot imgtec dot org> <8738mm3pgb dot fsf at talisman dot default> <alpine dot DEB dot 1 dot 10 dot 1311241820110 dot 21686 at tp dot orcam dot me dot uk> <0DA23CC379F5F945ACB41CF394B982774DAC1A at LEMAIL01 dot le dot imgtec dot org> <87fvq07ufx dot fsf at talisman dot default> <0DA23CC379F5F945ACB41CF394B982774DE91E at LEMAIL01 dot le dot imgtec dot org> <87vbysiu3a dot fsf at sandifor-thinkpad dot stglab dot manchester dot uk dot ibm dot com>
On Fri, 13 Dec 2013, Richard Sandiford wrote:
> Looks good, thanks, but is there any reason not to use mips_cp1_names_mips3264
> for all MIPS32 and MIPS64 targets? I realise some of them don't have an FPU,
> but if we see (presumably emulated) FPU instructions anyway, then I think we
> might as well follow the architecture names for the registers.
Rev. 1 FPUs only had the FIR, FCCR, FEXR, FENR and FCSR registers. Older
ISAs only had the FIR and FCSR registers. How about we have separate
lists just as with CP0? Furthermore I don't think these additional lists
should be a prerequisite for the acceptance of this patch.
> E.g.:
>
> Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
> > @@ -525,43 +571,43 @@ const struct mips_arch_choice mips_arch_choices[] =
> > { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
> > ISA_MIPS64 | INSN_SB1, ASE_MIPS3D,
> > mips_cp0_names_sb1,
> > mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
> > - mips_hwr_names_numeric },
> > + mips_cp1_names_numeric, mips_hwr_names_numeric },
>
> SB1 did have an FPU.
It was rev. 1 however.
> If you agree, then the patch is OK with every ISA_MIPS32* and ISA_MIPS64*
> entry having mips_cp1_names_mips3264. If not then let me know :-)
Shouldn't there be a complementing GAS part though?
Maciej