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[PATCH/ARM] PR 16722, support VLDR s/d0, =Imm
- From: Jiong Wang <jiong dot wang at arm dot com>
- To: Binutils <binutils at sourceware dot org>
- Date: Tue, 22 Apr 2014 13:46:07 +0100
- Subject: [PATCH/ARM] PR 16722, support VLDR s/d0, =Imm
- Authentication-results: sourceware.org; auth=none
LDR support load constants from literal pool or optimize to vmov, while no such support on VLDR. This patch fixes this issue.
the logic of this patch is
for VLDR s/d, =IMM, (currently no support for FPIMM)
if (s reg)
always spill to literal pool.
if (d reg)
if (IMM acceptable by vmov)
{
if (thumb_mode)
rewrite vldr d, #IMM to vmov.XX d, #IMM under thumb2 encoding.
else
rewrite under arm encoding.
}
else
spill to literal pool.
OK for trunk?
thanks.
PR target/16722
gas/
* config/tc-arm.c (add_to_lit_pool): Add one parameter 'nbytes'.
Support literal pool entry be 8 byte.
(s_ltorg): Likewise.
(enum lit_type): New enum type.
(encode_arm_cp_address): Generate literal pool entry if possible.
(move_or_literal_pool): Generate entry for vldr case.
(do_ldst): Use new enum type.
(do_ldstv4): Likewise.
(do_t_ldst): Likewise.
(neon_write_immbits): Support Thumb-2 mode.
gas/testsuite/
* gas/arm/ldconst.s: Add new cases for vldr.
* gas/arm/ldconst.d: Likewise.
* gas/arm/thumb2_pool.s: Likewise.
* gas/arm/thumb2_pool.d: Likewise.
--
Jiong
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 69299c7..1471fce 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -3180,20 +3180,24 @@ find_or_make_literal_pool (void)
structure to the relevant literal pool. */
static int
-add_to_lit_pool (void)
+add_to_lit_pool (int nbytes)
{
literal_pool * pool;
unsigned int entry;
+ unsigned int entry_for_relocate;
pool = find_or_make_literal_pool ();
/* Check if this literal value is already in the pool. */
- for (entry = 0; entry < pool->next_free_entry; entry ++)
+ for (entry = 0, entry_for_relocate = 0;
+ entry < pool->next_free_entry;
+ entry ++, entry_for_relocate++)
{
if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
&& (inst.reloc.exp.X_op == O_constant)
&& (pool->literals[entry].X_add_number
== inst.reloc.exp.X_add_number)
+ && (pool->literals[entry].X_md == nbytes)
&& (pool->literals[entry].X_unsigned
== inst.reloc.exp.X_unsigned))
break;
@@ -3205,8 +3209,12 @@ add_to_lit_pool (void)
&& (pool->literals[entry].X_add_symbol
== inst.reloc.exp.X_add_symbol)
&& (pool->literals[entry].X_op_symbol
- == inst.reloc.exp.X_op_symbol))
+ == inst.reloc.exp.X_op_symbol)
+ && (pool->literals[entry].X_md == nbytes))
break;
+
+ if (pool->literals[entry].X_md == 8)
+ entry_for_relocate++;
}
/* Do we need to create a new entry? */
@@ -3219,6 +3227,7 @@ add_to_lit_pool (void)
}
pool->literals[entry] = inst.reloc.exp;
+ pool->literals[entry].X_md = nbytes;
#ifdef OBJ_ELF
/* PR ld/12974: Record the location of the first source line to reference
this entry in the literal pool. If it turns out during linking that the
@@ -3231,7 +3240,7 @@ add_to_lit_pool (void)
}
inst.reloc.exp.X_op = O_symbol;
- inst.reloc.exp.X_add_number = ((int) entry) * 4;
+ inst.reloc.exp.X_add_number = ((int) entry_for_relocate) * 4;
inst.reloc.exp.X_add_symbol = pool->symbol;
return SUCCESS;
@@ -3314,7 +3323,6 @@ symbol_locate (symbolS * symbolP,
#endif /* DEBUG_SYMS */
}
-
static void
s_ltorg (int ignored ATTRIBUTE_UNUSED)
{
@@ -3356,7 +3364,8 @@ s_ltorg (int ignored ATTRIBUTE_UNUSED)
dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
#endif
/* First output the expression in the instruction to the pool. */
- emit_expr (&(pool->literals[entry]), 4); /* .word */
+ emit_expr (&(pool->literals[entry]),
+ pool->literals[entry].X_md); /* how many .word */
}
/* Mark the pool as empty. */
@@ -7375,6 +7384,14 @@ encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
}
}
+enum lit_type {
+ CONST_THUMB,
+ CONST_ARM,
+ CONST_VEC
+};
+
+static bfd_boolean move_or_literal_pool (int, enum lit_type, bfd_boolean);
+
/* inst.operands[i] was set up by parse_address. Encode it into an
ARM-format instruction. Reject all forms which cannot be encoded
into a coprocessor load/store instruction. If wb_ok is false,
@@ -7386,6 +7403,13 @@ encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
static int
encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
{
+ if (!inst.operands[i].isreg)
+ {
+ gas_assert (inst.operands[0].isvec);
+ if (move_or_literal_pool (0, /*lit_type=*/CONST_VEC, /*mode_3=*/FALSE))
+ return SUCCESS;
+ }
+
inst.instruction |= inst.operands[i].reg << 16;
gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
@@ -7440,6 +7464,11 @@ encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
return SUCCESS;
}
+static void neon_write_immbits (unsigned);
+static void neon_invert_size (unsigned *, unsigned *, int);
+static int neon_cmode_for_move_imm (unsigned, unsigned, int, unsigned *, int *,
+ int, enum neon_el_type);
+
/* inst.reloc.exp describes an "=expr" load pseudo-operation.
Determine whether it can be performed with a move instruction; if
it can, convert inst.instruction to that move instruction and
@@ -7450,9 +7479,12 @@ encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
inst.operands[i] describes the destination register. */
static bfd_boolean
-move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
+move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
{
unsigned long tbit;
+ bfd_boolean thumb_p = t == CONST_THUMB;
+ bfd_boolean arm_p = t == CONST_ARM;
+ bfd_boolean vec64_p = (t == CONST_VEC) && !inst.operands[i].issingle;
if (thumb_p)
tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
@@ -7469,7 +7501,7 @@ move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
inst.error = _("constant expression expected");
return TRUE;
}
- if (inst.reloc.exp.X_op == O_constant)
+ if (inst.reloc.exp.X_op == O_constant && !inst.operands[i].issingle)
{
if (thumb_p)
{
@@ -7481,7 +7513,7 @@ move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
return TRUE;
}
}
- else
+ else if (arm_p)
{
int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
if (value != FAIL)
@@ -7503,9 +7535,40 @@ move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
return TRUE;
}
}
+ else if (vec64_p)
+ {
+ int op = 0;
+ unsigned immbits = 0;
+ unsigned immlo = inst.reloc.exp.X_add_number & 0xFFFFFFFF;
+ unsigned immhi = (inst.reloc.exp.X_add_number >> 32) & 0xFFFFFFFF;
+ int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
+ &op, 64, NT_invtype);
+ if (cmode == FAIL)
+ {
+ neon_invert_size (&immlo, &immhi, 64);
+ op = !op;
+ cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
+ &op, 64, NT_invtype);
+ }
+ if (cmode != FAIL)
+ {
+ inst.instruction = (inst.instruction & 0x40F000)
+ | (1 << 23)
+ | (cmode << 8)
+ | (op << 5)
+ | (1 << 4);
+ if (thumb_mode)
+ inst.instruction |= (0x7 << 29) | (0xF << 24);
+ else
+ inst.instruction |= (0xF << 28) | (0x1 << 25);
+ neon_write_immbits (immbits);
+ return TRUE;
+ }
+ }
}
- if (add_to_lit_pool () == FAIL)
+ if (add_to_lit_pool ((!inst.operands[i].isvec
+ || inst.operands[i].issingle) ? 4 : 8) == FAIL)
{
inst.error = _("literal pool insertion failed");
return TRUE;
@@ -8252,7 +8315,7 @@ do_ldst (void)
{
inst.instruction |= inst.operands[0].reg << 12;
if (!inst.operands[1].isreg)
- if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
+ if (move_or_literal_pool (0, /*lit_type=*/CONST_ARM, /*mode_3=*/FALSE))
return;
encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
check_ldr_r15_aligned ();
@@ -8285,7 +8348,7 @@ do_ldstv4 (void)
constraint (inst.operands[0].reg == REG_PC, BAD_PC);
inst.instruction |= inst.operands[0].reg << 12;
if (!inst.operands[1].isreg)
- if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
+ if (move_or_literal_pool (0, /*lit_type=*/CONST_ARM, /*mode_3=*/TRUE))
return;
encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
}
@@ -10829,7 +10892,7 @@ do_t_ldst (void)
{
if (opcode <= 0xffff)
inst.instruction = THUMB_OP32 (opcode);
- if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
+ if (move_or_literal_pool (0, /*lit_type=*/CONST_THUMB, /*mode_3=*/FALSE))
return;
}
if (inst.operands[1].isreg
@@ -10935,7 +10998,7 @@ do_t_ldst (void)
inst.instruction = THUMB_OP16 (inst.instruction);
if (!inst.operands[1].isreg)
- if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
+ if (move_or_literal_pool (0, /*lit_type=*/CONST_THUMB, /*mode_3=*/FALSE))
return;
constraint (!inst.operands[1].preind
@@ -13967,7 +14030,7 @@ neon_write_immbits (unsigned immbits)
{
inst.instruction |= immbits & 0xf;
inst.instruction |= ((immbits >> 4) & 0x7) << 16;
- inst.instruction |= ((immbits >> 7) & 0x1) << 24;
+ inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
}
/* Invert low-order SIZE bits of XHI:XLO. */
diff --git a/gas/testsuite/gas/arm/ldconst.d b/gas/testsuite/gas/arm/ldconst.d
index 3d06378..9480897 100644
--- a/gas/testsuite/gas/arm/ldconst.d
+++ b/gas/testsuite/gas/arm/ldconst.d
@@ -25,3 +25,231 @@ Disassembly of section .text:
0+44 <[^>]*> 43e0b0ff ? mvnmi fp, #255 ; 0xff
0+48 <[^>]*> 451fb004 ? ldrmi fp, \[pc, #-4\] ; 0+4c <[^>]*>
0+4c <[^>]*> 0000fff0 ? .*
+0+50 <[^>]*> ed9f0a0e ? vldr s0, \[pc, #56\] ; 0+90 <[^>]*>
+0+54 <[^>]*> ed9f7a0d ? vldr s14, \[pc, #52\] ; 0+90 <[^>]*>
+0+58 <[^>]*> ed9fea0c ? vldr s28, \[pc, #48\] ; 0+90 <[^>]*>
+0+5c <[^>]*> eddffa0b ? vldr s31, \[pc, #44\] ; 0+90 <[^>]*>
+0+60 <[^>]*> ed9f0a0b ? vldr s0, \[pc, #44\] ; 0+94 <[^>]*>
+0+64 <[^>]*> ed9f7a0a ? vldr s14, \[pc, #40\] ; 0+94 <[^>]*>
+0+68 <[^>]*> ed9fea09 ? vldr s28, \[pc, #36\] ; 0+94 <[^>]*>
+0+6c <[^>]*> eddffa08 ? vldr s31, \[pc, #32\] ; 0+94 <[^>]*>
+0+70 <[^>]*> ed9f0a08 ? vldr s0, \[pc, #32\] ; 0+98 <[^>]*>
+0+74 <[^>]*> ed9f7a07 ? vldr s14, \[pc, #28\] ; 0+98 <[^>]*>
+0+78 <[^>]*> ed9fea06 ? vldr s28, \[pc, #24\] ; 0+98 <[^>]*>
+0+7c <[^>]*> eddffa05 ? vldr s31, \[pc, #20\] ; 0+98 <[^>]*>
+0+80 <[^>]*> ed9f0a05 ? vldr s0, \[pc, #20\] ; 0+9c <[^>]*>
+0+84 <[^>]*> ed9f7a04 ? vldr s14, \[pc, #16\] ; 0+9c <[^>]*>
+0+88 <[^>]*> ed9fea03 ? vldr s28, \[pc, #12\] ; 0+9c <[^>]*>
+0+8c <[^>]*> eddffa02 ? vldr s31, \[pc, #8\] ; 0+9c <[^>]*>
+0+90 <[^>]*> 00000000 ? .*
+0+94 <[^>]*> ff000000 ? .*
+0+98 <[^>]*> ffffffff ? .*
+0+9c <[^>]*> 0fff0000 ? .*
+0+a0 <[^>]*> ed9f0a0e ? vldr s0, \[pc, #56\] ; 0+e0 <[^>]*>
+0+a4 <[^>]*> ed9f7a0d ? vldr s14, \[pc, #52\] ; 0+e0 <[^>]*>
+0+a8 <[^>]*> ed9fea0c ? vldr s28, \[pc, #48\] ; 0+e0 <[^>]*>
+0+ac <[^>]*> eddffa0b ? vldr s31, \[pc, #44\] ; 0+e0 <[^>]*>
+0+b0 <[^>]*> ed9f0a0b ? vldr s0, \[pc, #44\] ; 0+e4 <[^>]*>
+0+b4 <[^>]*> ed9f7a0a ? vldr s14, \[pc, #40\] ; 0+e4 <[^>]*>
+0+b8 <[^>]*> ed9fea09 ? vldr s28, \[pc, #36\] ; 0+e4 <[^>]*>
+0+bc <[^>]*> eddffa08 ? vldr s31, \[pc, #32\] ; 0+e4 <[^>]*>
+0+c0 <[^>]*> ed9f0a08 ? vldr s0, \[pc, #32\] ; 0+e8 <[^>]*>
+0+c4 <[^>]*> ed9f7a07 ? vldr s14, \[pc, #28\] ; 0+e8 <[^>]*>
+0+c8 <[^>]*> ed9fea06 ? vldr s28, \[pc, #24\] ; 0+e8 <[^>]*>
+0+cc <[^>]*> eddffa05 ? vldr s31, \[pc, #20\] ; 0+e8 <[^>]*>
+0+d0 <[^>]*> ed9f0a05 ? vldr s0, \[pc, #20\] ; 0+ec <[^>]*>
+0+d4 <[^>]*> ed9f7a04 ? vldr s14, \[pc, #16\] ; 0+ec <[^>]*>
+0+d8 <[^>]*> ed9fea03 ? vldr s28, \[pc, #12\] ; 0+ec <[^>]*>
+0+dc <[^>]*> eddffa02 ? vldr s31, \[pc, #8\] ; 0+ec <[^>]*>
+0+e0 <[^>]*> 00000000 ? .*
+0+e4 <[^>]*> 00ff0000 ? .*
+0+e8 <[^>]*> ff00ffff ? .*
+0+ec <[^>]*> 00fff000 ? .*
+0+f0 <[^>]*> 0d9f0a0e ? vldreq s0, \[pc, #56\] ; 0+130 <[^>]*>
+0+f4 <[^>]*> 0d9f7a0d ? vldreq s14, \[pc, #52\] ; 0+130 <[^>]*>
+0+f8 <[^>]*> 0d9fea0c ? vldreq s28, \[pc, #48\] ; 0+130 <[^>]*>
+0+fc <[^>]*> 0ddffa0b ? vldreq s31, \[pc, #44\] ; 0+130 <[^>]*>
+0+100 <[^>]*> 0d9f0a0b ? vldreq s0, \[pc, #44\] ; 0+134 <[^>]*>
+0+104 <[^>]*> 0d9f7a0a ? vldreq s14, \[pc, #40\] ; 0+134 <[^>]*>
+0+108 <[^>]*> 0d9fea09 ? vldreq s28, \[pc, #36\] ; 0+134 <[^>]*>
+0+10c <[^>]*> 0ddffa08 ? vldreq s31, \[pc, #32\] ; 0+134 <[^>]*>
+0+110 <[^>]*> 0d9f0a08 ? vldreq s0, \[pc, #32\] ; 0+138 <[^>]*>
+0+114 <[^>]*> 0d9f7a07 ? vldreq s14, \[pc, #28\] ; 0+138 <[^>]*>
+0+118 <[^>]*> 0d9fea06 ? vldreq s28, \[pc, #24\] ; 0+138 <[^>]*>
+0+11c <[^>]*> 0ddffa05 ? vldreq s31, \[pc, #20\] ; 0+138 <[^>]*>
+0+120 <[^>]*> 0d9f0a05 ? vldreq s0, \[pc, #20\] ; 0+13c <[^>]*>
+0+124 <[^>]*> 0d9f7a04 ? vldreq s14, \[pc, #16\] ; 0+13c <[^>]*>
+0+128 <[^>]*> 0d9fea03 ? vldreq s28, \[pc, #12\] ; 0+13c <[^>]*>
+0+12c <[^>]*> 0ddffa02 ? vldreq s31, \[pc, #8\] ; 0+13c <[^>]*>
+0+130 <[^>]*> 00000000 ? .*
+0+134 <[^>]*> 0000ff00 ? .*
+0+138 <[^>]*> ffff00ff ? .*
+0+13c <[^>]*> 000fff00 ? .*
+0+140 <[^>]*> 4d9f0a0e ? vldrmi s0, \[pc, #56\] ; 0+180 <[^>]*>
+0+144 <[^>]*> 4d9f7a0d ? vldrmi s14, \[pc, #52\] ; 0+180 <[^>]*>
+0+148 <[^>]*> 4d9fea0c ? vldrmi s28, \[pc, #48\] ; 0+180 <[^>]*>
+0+14c <[^>]*> 4ddffa0b ? vldrmi s31, \[pc, #44\] ; 0+180 <[^>]*>
+0+150 <[^>]*> 4d9f0a0b ? vldrmi s0, \[pc, #44\] ; 0+184 <[^>]*>
+0+154 <[^>]*> 4d9f7a0a ? vldrmi s14, \[pc, #40\] ; 0+184 <[^>]*>
+0+158 <[^>]*> 4d9fea09 ? vldrmi s28, \[pc, #36\] ; 0+184 <[^>]*>
+0+15c <[^>]*> 4ddffa08 ? vldrmi s31, \[pc, #32\] ; 0+184 <[^>]*>
+0+160 <[^>]*> 4d9f0a08 ? vldrmi s0, \[pc, #32\] ; 0+188 <[^>]*>
+0+164 <[^>]*> 4d9f7a07 ? vldrmi s14, \[pc, #28\] ; 0+188 <[^>]*>
+0+168 <[^>]*> 4d9fea06 ? vldrmi s28, \[pc, #24\] ; 0+188 <[^>]*>
+0+16c <[^>]*> 4ddffa05 ? vldrmi s31, \[pc, #20\] ; 0+188 <[^>]*>
+0+170 <[^>]*> 4d9f0a05 ? vldrmi s0, \[pc, #20\] ; 0+18c <[^>]*>
+0+174 <[^>]*> 4d9f7a04 ? vldrmi s14, \[pc, #16\] ; 0+18c <[^>]*>
+0+178 <[^>]*> 4d9fea03 ? vldrmi s28, \[pc, #12\] ; 0+18c <[^>]*>
+0+17c <[^>]*> 4ddffa02 ? vldrmi s31, \[pc, #8\] ; 0+18c <[^>]*>
+0+180 <[^>]*> 00000000 ? .*
+0+184 <[^>]*> 000000ff ? .*
+0+188 <[^>]*> ffffff00 ? .*
+0+18c <[^>]*> 0000fff0 ? .*
+0+190 <[^>]*> f2800e30 ? vmov.i64 d0, #0x0000000000000000
+0+194 <[^>]*> f280ee30 ? vmov.i64 d14, #0x0000000000000000
+0+198 <[^>]*> f2c0ce30 ? vmov.i64 d28, #0x0000000000000000
+0+19c <[^>]*> f2c0fe30 ? vmov.i64 d31, #0x0000000000000000
+0+1a0 <[^>]*> ed9f0b0a ? vldr d0, \[pc, #40\] ; 0+1d0 <[^>]*>
+0+1a4 <[^>]*> ed9feb09 ? vldr d14, \[pc, #36\] ; 0+1d0 <[^>]*>
+0+1a8 <[^>]*> eddfcb08 ? vldr d28, \[pc, #32\] ; 0+1d0 <[^>]*>
+0+1ac <[^>]*> eddffb07 ? vldr d31, \[pc, #28\] ; 0+1d0 <[^>]*>
+0+1b0 <[^>]*> f3870e3f ? vmov.i64 d0, #0xffffffffffffffff
+0+1b4 <[^>]*> f387ee3f ? vmov.i64 d14, #0xffffffffffffffff
+0+1b8 <[^>]*> f3c7ce3f ? vmov.i64 d28, #0xffffffffffffffff
+0+1bc <[^>]*> f3c7fe3f ? vmov.i64 d31, #0xffffffffffffffff
+0+1c0 <[^>]*> ed9f0b04 ? vldr d0, \[pc, #16\] ; 0+1d8 <[^>]*>
+0+1c4 <[^>]*> ed9feb03 ? vldr d14, \[pc, #12\] ; 0+1d8 <[^>]*>
+0+1c8 <[^>]*> eddfcb02 ? vldr d28, \[pc, #8\] ; 0+1d8 <[^>]*>
+0+1cc <[^>]*> eddffb01 ? vldr d31, \[pc, #4\] ; 0+1d8 <[^>]*>
+0+1d0 <[^>]*> ca000000 ? .*
+0+1d4 <[^>]*> 00000000 ? .*
+0+1d8 <[^>]*> 0fff0000 ? .*
+0+1dc <[^>]*> 00000000 ? .*
+0+1e0 <[^>]*> f2800e30 ? vmov.i64 d0, #0x0000000000000000
+0+1e4 <[^>]*> f280ee30 ? vmov.i64 d14, #0x0000000000000000
+0+1e8 <[^>]*> f2c0ce30 ? vmov.i64 d28, #0x0000000000000000
+0+1ec <[^>]*> f2c0fe30 ? vmov.i64 d31, #0x0000000000000000
+0+1f0 <[^>]*> f2800e34 ? vmov.i64 d0, #0x0000000000ff0000
+0+1f4 <[^>]*> f280ee34 ? vmov.i64 d14, #0x0000000000ff0000
+0+1f8 <[^>]*> f2c0ce34 ? vmov.i64 d28, #0x0000000000ff0000
+0+1fc <[^>]*> f2c0fe34 ? vmov.i64 d31, #0x0000000000ff0000
+0+200 <[^>]*> f2800e39 ? vmov.i64 d0, #0x00000000ff0000ff
+0+204 <[^>]*> f280ee39 ? vmov.i64 d14, #0x00000000ff0000ff
+0+208 <[^>]*> f2c0ce39 ? vmov.i64 d28, #0x00000000ff0000ff
+0+20c <[^>]*> f2c0fe39 ? vmov.i64 d31, #0x00000000ff0000ff
+0+210 <[^>]*> ed9f0b02 ? vldr d0, \[pc, #8\] ; 0+220 <[^>]*>
+0+214 <[^>]*> ed9feb01 ? vldr d14, \[pc, #4\] ; 0+220 <[^>]*>
+0+218 <[^>]*> eddfcb00 ? vldr d28, \[pc\] ; 0+220 <[^>]*>
+0+21c <[^>]*> ed5ffb01 ? vldr d31, \[pc, #-4\] ; 0+220 <[^>]*>
+0+220 <[^>]*> 00fff000 ? .*
+0+224 <[^>]*> 00000000 ? .*
+0+228 <[^>]*> f2800e30 ? vmov.i64 d0, #0x0000000000000000
+0+22c <[^>]*> f280ee30 ? vmov.i64 d14, #0x0000000000000000
+0+230 <[^>]*> f2c0ce30 ? vmov.i64 d28, #0x0000000000000000
+0+234 <[^>]*> f2c0fe30 ? vmov.i64 d31, #0x0000000000000000
+0+238 <[^>]*> f2800e32 ? vmov.i64 d0, #0x000000000000ff00
+0+23c <[^>]*> f280ee32 ? vmov.i64 d14, #0x000000000000ff00
+0+240 <[^>]*> f2c0ce32 ? vmov.i64 d28, #0x000000000000ff00
+0+244 <[^>]*> f2c0fe32 ? vmov.i64 d31, #0x000000000000ff00
+0+248 <[^>]*> f2800e3d ? vmov.i64 d0, #0x00000000ffff00ff
+0+24c <[^>]*> f280ee3d ? vmov.i64 d14, #0x00000000ffff00ff
+0+250 <[^>]*> f2c0ce3d ? vmov.i64 d28, #0x00000000ffff00ff
+0+254 <[^>]*> f2c0fe3d ? vmov.i64 d31, #0x00000000ffff00ff
+0+258 <[^>]*> 0d9f0b02 ? vldreq d0, \[pc, #8\] ; 0+268 <[^>]*>
+0+25c <[^>]*> 0d9feb01 ? vldreq d14, \[pc, #4\] ; 0+268 <[^>]*>
+0+260 <[^>]*> 0ddfcb00 ? vldreq d28, \[pc\] ; 0+268 <[^>]*>
+0+264 <[^>]*> 0d5ffb01 ? vldreq d31, \[pc, #-4\] ; 0+268 <[^>]*>
+0+268 <[^>]*> 000fff00 ? .*
+0+26c <[^>]*> 00000000 ? .*
+0+270 <[^>]*> f2800e30 ? vmov.i64 d0, #0x0000000000000000
+0+274 <[^>]*> f280ee30 ? vmov.i64 d14, #0x0000000000000000
+0+278 <[^>]*> f2c0ce30 ? vmov.i64 d28, #0x0000000000000000
+0+27c <[^>]*> f2c0fe30 ? vmov.i64 d31, #0x0000000000000000
+0+280 <[^>]*> f2800e31 ? vmov.i64 d0, #0x00000000000000ff
+0+284 <[^>]*> f280ee31 ? vmov.i64 d14, #0x00000000000000ff
+0+288 <[^>]*> f2c0ce31 ? vmov.i64 d28, #0x00000000000000ff
+0+28c <[^>]*> f2c0fe31 ? vmov.i64 d31, #0x00000000000000ff
+0+290 <[^>]*> f2800e3e ? vmov.i64 d0, #0x00000000ffffff00
+0+294 <[^>]*> f280ee3e ? vmov.i64 d14, #0x00000000ffffff00
+0+298 <[^>]*> f2c0ce3e ? vmov.i64 d28, #0x00000000ffffff00
+0+29c <[^>]*> f2c0fe3e ? vmov.i64 d31, #0x00000000ffffff00
+0+2a0 <[^>]*> f2800e33 ? vmov.i64 d0, #0x000000000000ffff
+0+2a4 <[^>]*> f280ee33 ? vmov.i64 d14, #0x000000000000ffff
+0+2a8 <[^>]*> f2c0ce33 ? vmov.i64 d28, #0x000000000000ffff
+0+2ac <[^>]*> f2c0fe33 ? vmov.i64 d31, #0x000000000000ffff
+0+2b0 <[^>]*> f2800e30 ? vmov.i64 d0, #0x0000000000000000
+0+2b4 <[^>]*> f280ee30 ? vmov.i64 d14, #0x0000000000000000
+0+2b8 <[^>]*> f2c0ce30 ? vmov.i64 d28, #0x0000000000000000
+0+2bc <[^>]*> f2c0fe30 ? vmov.i64 d31, #0x0000000000000000
+0+2c0 <[^>]*> f3800e30 ? vmov.i64 d0, #0xff00000000000000
+0+2c4 <[^>]*> f380ee30 ? vmov.i64 d14, #0xff00000000000000
+0+2c8 <[^>]*> f3c0ce30 ? vmov.i64 d28, #0xff00000000000000
+0+2cc <[^>]*> f3c0fe30 ? vmov.i64 d31, #0xff00000000000000
+0+2d0 <[^>]*> f3870e3f ? vmov.i64 d0, #0xffffffffffffffff
+0+2d4 <[^>]*> f387ee3f ? vmov.i64 d14, #0xffffffffffffffff
+0+2d8 <[^>]*> f3c7ce3f ? vmov.i64 d28, #0xffffffffffffffff
+0+2dc <[^>]*> f3c7fe3f ? vmov.i64 d31, #0xffffffffffffffff
+0+2e0 <[^>]*> ed9f0b02 ? vldr d0, \[pc, #8\] ; 0+2f0 <[^>]*>
+0+2e4 <[^>]*> ed9feb01 ? vldr d14, \[pc, #4\] ; 0+2f0 <[^>]*>
+0+2e8 <[^>]*> eddfcb00 ? vldr d28, \[pc\] ; 0+2f0 <[^>]*>
+0+2ec <[^>]*> ed5ffb01 ? vldr d31, \[pc, #-4\] ; 0+2f0 <[^>]*>
+0+2f0 <[^>]*> 00000000 ? .*
+0+2f4 <[^>]*> 0fff0000 ? .*
+0+2f8 <[^>]*> f2800e30 ? vmov.i64 d0, #0x0000000000000000
+0+2fc <[^>]*> f280ee30 ? vmov.i64 d14, #0x0000000000000000
+0+300 <[^>]*> f2c0ce30 ? vmov.i64 d28, #0x0000000000000000
+0+304 <[^>]*> f2c0fe30 ? vmov.i64 d31, #0x0000000000000000
+0+308 <[^>]*> ed9f0b0a ? vldr d0, \[pc, #40\] ; 0+338 <[^>]*>
+0+30c <[^>]*> ed9feb09 ? vldr d14, \[pc, #36\] ; 0+338 <[^>]*>
+0+310 <[^>]*> eddfcb08 ? vldr d28, \[pc, #32\] ; 0+338 <[^>]*>
+0+314 <[^>]*> eddffb07 ? vldr d31, \[pc, #28\] ; 0+338 <[^>]*>
+0+318 <[^>]*> ed9f0b08 ? vldr d0, \[pc, #32\] ; 0+340 <[^>]*>
+0+31c <[^>]*> ed9feb07 ? vldr d14, \[pc, #28\] ; 0+340 <[^>]*>
+0+320 <[^>]*> eddfcb06 ? vldr d28, \[pc, #24\] ; 0+340 <[^>]*>
+0+324 <[^>]*> eddffb05 ? vldr d31, \[pc, #20\] ; 0+340 <[^>]*>
+0+328 <[^>]*> ed9f0b06 ? vldr d0, \[pc, #24\] ; 0+348 <[^>]*>
+0+32c <[^>]*> ed9feb05 ? vldr d14, \[pc, #20\] ; 0+348 <[^>]*>
+0+330 <[^>]*> eddfcb04 ? vldr d28, \[pc, #16\] ; 0+348 <[^>]*>
+0+334 <[^>]*> eddffb03 ? vldr d31, \[pc, #12\] ; 0+348 <[^>]*>
+0+338 <[^>]*> 00000000 ? .*
+0+33c <[^>]*> 000ff000 ? .*
+0+340 <[^>]*> f0000000 ? .*
+0+344 <[^>]*> 0ff00fff ? .*
+0+348 <[^>]*> 00000000 ? .*
+0+34c <[^>]*> 000fff00 ? .*
+0+350 <[^>]*> f2800e30 ? vmov.i64 d0, #0x0000000000000000
+0+354 <[^>]*> f280ee30 ? vmov.i64 d14, #0x0000000000000000
+0+358 <[^>]*> f2c0ce30 ? vmov.i64 d28, #0x0000000000000000
+0+35c <[^>]*> f2c0fe30 ? vmov.i64 d31, #0x0000000000000000
+0+360 <[^>]*> f2820e30 ? vmov.i64 d0, #0x0000ff0000000000
+0+364 <[^>]*> f282ee30 ? vmov.i64 d14, #0x0000ff0000000000
+0+368 <[^>]*> f2c2ce30 ? vmov.i64 d28, #0x0000ff0000000000
+0+36c <[^>]*> f2c2fe30 ? vmov.i64 d31, #0x0000ff0000000000
+0+370 <[^>]*> f3850e30 ? vmov.i64 d0, #0xffff00ff00000000
+0+374 <[^>]*> f385ee30 ? vmov.i64 d14, #0xffff00ff00000000
+0+378 <[^>]*> f3c5ce30 ? vmov.i64 d28, #0xffff00ff00000000
+0+37c <[^>]*> f3c5fe30 ? vmov.i64 d31, #0xffff00ff00000000
+0+380 <[^>]*> 0d9f0b02 ? vldreq d0, \[pc, #8\] ; 0+390 <[^>]*>
+0+384 <[^>]*> 0d9feb01 ? vldreq d14, \[pc, #4\] ; 0+390 <[^>]*>
+0+388 <[^>]*> 0ddfcb00 ? vldreq d28, \[pc\] ; 0+390 <[^>]*>
+0+38c <[^>]*> 0d5ffb01 ? vldreq d31, \[pc, #-4\] ; 0+390 <[^>]*>
+0+390 <[^>]*> 00000000 ? .*
+0+394 <[^>]*> 000fff00 ? .*
+0+398 <[^>]*> f2800e30 ? vmov.i64 d0, #0x0000000000000000
+0+39c <[^>]*> f280ee30 ? vmov.i64 d14, #0x0000000000000000
+0+3a0 <[^>]*> f2c0ce30 ? vmov.i64 d28, #0x0000000000000000
+0+3a4 <[^>]*> f2c0fe30 ? vmov.i64 d31, #0x0000000000000000
+0+3a8 <[^>]*> f2810e30 ? vmov.i64 d0, #0x000000ff00000000
+0+3ac <[^>]*> f281ee30 ? vmov.i64 d14, #0x000000ff00000000
+0+3b0 <[^>]*> f2c1ce30 ? vmov.i64 d28, #0x000000ff00000000
+0+3b4 <[^>]*> f2c1fe30 ? vmov.i64 d31, #0x000000ff00000000
+0+3b8 <[^>]*> f3860e30 ? vmov.i64 d0, #0xffffff0000000000
+0+3bc <[^>]*> f386ee30 ? vmov.i64 d14, #0xffffff0000000000
+0+3c0 <[^>]*> f3c6ce30 ? vmov.i64 d28, #0xffffff0000000000
+0+3c4 <[^>]*> f3c6fe30 ? vmov.i64 d31, #0xffffff0000000000
+0+3c8 <[^>]*> 4d9f0b02 ? vldrmi d0, \[pc, #8\] ; 0+3d8 <[^>]*>
+0+3cc <[^>]*> 4d9feb01 ? vldrmi d14, \[pc, #4\] ; 0+3d8 <[^>]*>
+0+3d0 <[^>]*> 4ddfcb00 ? vldrmi d28, \[pc\] ; 0+3d8 <[^>]*>
+0+3d4 <[^>]*> 4d5ffb01 ? vldrmi d31, \[pc, #-4\] ; 0+3d8 <[^>]*>
+0+3d8 <[^>]*> 00000000 ? .*
+0+3dc <[^>]*> 0000fff0 ? .*
diff --git a/gas/testsuite/gas/arm/ldconst.s b/gas/testsuite/gas/arm/ldconst.s
index 1b6aca9..5eaa7cc 100644
--- a/gas/testsuite/gas/arm/ldconst.s
+++ b/gas/testsuite/gas/arm/ldconst.s
@@ -1,5 +1,5 @@
-@ Test file for ARM/GAS -- ldr reg, =... expressions.
-
+@ Test file for ARM/GAS -- ldr/vldr reg, =... expressions.
+.fpu neon
.text
.align
foo:
@@ -26,3 +26,95 @@ foo:
ldrmi r11, =0xffffff00
ldrmi r11, =0x0000fff0
.pool
+
+ # test both low and high index of the
+ # Advanced SIMD and Floating-point reg.
+ .macro vlxr regtype const
+ .irp regindex, 0, 14, 28, 31
+ vldr \regtype\regindex, \const
+ .endr
+ .endm
+
+ .macro vlxreq regtype const
+ .irp regindex, 0, 14, 28, 31
+ vldreq \regtype\regindex, \const
+ .endr
+ .endm
+
+ .macro vlxrmi regtype const
+ .irp regindex, 0, 14, 28, 31
+ vldrmi \regtype\regindex, \const
+ .endr
+ .endm
+
+ vlxr s "=0"
+ vlxr s "=0xff000000"
+ vlxr s "=-1"
+ vlxr s "=0x0fff0000"
+ .pool
+
+ vlxr s "=0"
+ vlxr s "=0x00ff0000"
+ vlxr s "=0xff00ffff"
+ vlxr s "=0x00fff000"
+ .pool
+
+ vlxreq s "=0"
+ vlxreq s "=0x0000ff00"
+ vlxreq s "=0xffff00ff"
+ vlxreq s "=0x000fff00"
+ .pool
+
+ vlxrmi s "=0"
+ vlxrmi s "=0x000000ff"
+ vlxrmi s "=0xffffff00"
+ vlxrmi s "=0x0000fff0"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0xca000000"
+ vlxr d "=-1"
+ vlxr d "=0x0fff0000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0x00ff0000"
+ vlxr d "=0xff0000ff"
+ vlxr d "=0x00fff000"
+ .pool
+
+ vlxreq d "=0"
+ vlxreq d "=0x0000ff00"
+ vlxreq d "=0xffff00ff"
+ vlxreq d "=0x000fff00"
+ .pool
+
+ vlxrmi d "=0"
+ vlxrmi d "=0x000000ff"
+ vlxrmi d "=0xffffff00"
+ vlxrmi d "=0x0000ffff"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0xff00000000000000"
+ vlxr d "=-1"
+ vlxr d "=0x0fff000000000000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0x00ff00000000000"
+ vlxr d "=0xff00ffff0000000"
+ vlxr d "=0x00fff0000000000"
+ .pool
+
+ vlxreq d "=0"
+ vlxreq d "=0x0000ff0000000000"
+ vlxreq d "=0xffff00ff00000000"
+ vlxreq d "=0x000fff0000000000"
+ .pool
+
+ vlxrmi d "=0"
+ vlxrmi d "=0x000000ff00000000"
+ vlxrmi d "=0xffffff0000000000"
+ vlxrmi d "=0x0000fff000000000"
+ .pool
diff --git a/gas/testsuite/gas/arm/thumb2_pool.d b/gas/testsuite/gas/arm/thumb2_pool.d
index 4d6ce44..272a5d4 100644
--- a/gas/testsuite/gas/arm/thumb2_pool.d
+++ b/gas/testsuite/gas/arm/thumb2_pool.d
@@ -14,3 +14,119 @@ Disassembly of section .text:
0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] ; 00+14 <[^>]+>
0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] ; \(00+14 <[^>]+>\)
0+014 <[^>]+> 12345678 ? .word 0x12345678
+0+018 <[^>]+> ed9f 0a0f vldr s0, \[pc, #60\] ; 00+58 <[^>]*>
+0+01c <[^>]+> ed9f 7a0e vldr s14, \[pc, #56\] ; 00+58 <[^>]*>
+0+020 <[^>]+> ed9f ea0d vldr s28, \[pc, #52\] ; 00+58 <[^>]*>
+0+024 <[^>]+> eddf fa0c vldr s31, \[pc, #48\] ; 00+58 <[^>]*>
+0+028 <[^>]+> ed9f 0a0c vldr s0, \[pc, #48\] ; 00+5c <[^>]*>
+0+02c <[^>]+> ed9f 7a0b vldr s14, \[pc, #44\] ; 00+5c <[^>]*>
+0+030 <[^>]+> ed9f ea0a vldr s28, \[pc, #40\] ; 00+5c <[^>]*>
+0+034 <[^>]+> eddf fa09 vldr s31, \[pc, #36\] ; 00+5c <[^>]*>
+0+038 <[^>]+> ed9f 0a09 vldr s0, \[pc, #36\] ; 00+60 <[^>]*>
+0+03c <[^>]+> ed9f 7a08 vldr s14, \[pc, #32\] ; 00+60 <[^>]*>
+0+040 <[^>]+> ed9f ea07 vldr s28, \[pc, #28\] ; 00+60 <[^>]*>
+0+044 <[^>]+> eddf fa06 vldr s31, \[pc, #24\] ; 00+60 <[^>]*>
+0+048 <[^>]+> ed9f 0a06 vldr s0, \[pc, #24\] ; 00+64 <[^>]*>
+0+04c <[^>]+> ed9f 7a05 vldr s14, \[pc, #20\] ; 00+64 <[^>]*>
+0+050 <[^>]+> ed9f ea04 vldr s28, \[pc, #16\] ; 00+64 <[^>]*>
+0+054 <[^>]+> eddf fa03 vldr s31, \[pc, #12\] ; 00+64 <[^>]*>
+0+058 <[^>]+> 00000000 .word 0x00000000
+0+05c <[^>]+> ff000000 .word 0xff000000
+0+060 <[^>]+> ffffffff .word 0xffffffff
+0+064 <[^>]+> 0fff0000 .word 0x0fff0000
+0+068 <[^>]+> ed9f 0a0f vldr s0, \[pc, #60\] ; 00+a8 <[^>]*>
+0+06c <[^>]+> ed9f 7a0e vldr s14, \[pc, #56\] ; 00+a8 <[^>]*>
+0+070 <[^>]+> ed9f ea0d vldr s28, \[pc, #52\] ; 00+a8 <[^>]*>
+0+074 <[^>]+> eddf fa0c vldr s31, \[pc, #48\] ; 00+a8 <[^>]*>
+0+078 <[^>]+> ed9f 0a0c vldr s0, \[pc, #48\] ; 00+ac <[^>]*>
+0+07c <[^>]+> ed9f 7a0b vldr s14, \[pc, #44\] ; 00+ac <[^>]*>
+0+080 <[^>]+> ed9f ea0a vldr s28, \[pc, #40\] ; 00+ac <[^>]*>
+0+084 <[^>]+> eddf fa09 vldr s31, \[pc, #36\] ; 00+ac <[^>]*>
+0+088 <[^>]+> ed9f 0a09 vldr s0, \[pc, #36\] ; 00+b0 <[^>]*>
+0+08c <[^>]+> ed9f 7a08 vldr s14, \[pc, #32\] ; 00+b0 <[^>]*>
+0+090 <[^>]+> ed9f ea07 vldr s28, \[pc, #28\] ; 00+b0 <[^>]*>
+0+094 <[^>]+> eddf fa06 vldr s31, \[pc, #24\] ; 00+b0 <[^>]*>
+0+098 <[^>]+> ed9f 0a06 vldr s0, \[pc, #24\] ; 00+b4 <[^>]*>
+0+09c <[^>]+> ed9f 7a05 vldr s14, \[pc, #20\] ; 00+b4 <[^>]*>
+0+0a0 <[^>]+> ed9f ea04 vldr s28, \[pc, #16\] ; 00+b4 <[^>]*>
+0+0a4 <[^>]+> eddf fa03 vldr s31, \[pc, #12\] ; 00+b4 <[^>]*>
+0+0a8 <[^>]+> 00000000 .word 0x00000000
+0+0ac <[^>]+> 00ff0000 .word 0x00ff0000
+0+0b0 <[^>]+> ff00ffff .word 0xff00ffff
+0+0b4 <[^>]+> 00fff000 .word 0x00fff000
+0+0b8 <[^>]+> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+0+0bc <[^>]+> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+0+0c0 <[^>]+> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+0+0c4 <[^>]+> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+0+0c8 <[^>]+> ed9f 0b0b vldr d0, \[pc, #44\] ; 00+f8 <[^>]*>
+0+0cc <[^>]+> ed9f eb0a vldr d14, \[pc, #40\] ; 00+f8 <[^>]*>
+0+0d0 <[^>]+> eddf cb09 vldr d28, \[pc, #36\] ; 00+f8 <[^>]*>
+0+0d4 <[^>]+> eddf fb08 vldr d31, \[pc, #32\] ; 00+f8 <[^>]*>
+0+0d8 <[^>]+> ff87 0e3f vmov.i64 d0, #0xffffffffffffffff
+0+0dc <[^>]+> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
+0+0e0 <[^>]+> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
+0+0e4 <[^>]+> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
+0+0e8 <[^>]+> ed9f 0b05 vldr d0, \[pc, #20\] ; 00+100 <[^>]*>
+0+0ec <[^>]+> ed9f eb04 vldr d14, \[pc, #16\] ; 00+100 <[^>]*>
+0+0f0 <[^>]+> eddf cb03 vldr d28, \[pc, #12\] ; 00+100 <[^>]*>
+0+0f4 <[^>]+> eddf fb02 vldr d31, \[pc, #8\] ; 00+100 <[^>]*>
+0+0f8 <[^>]+> ca000000 .word 0xca000000
+0+0fc <[^>]+> 00000000 .word 0x00000000
+0+100 <[^>]+> 0fff0000 .word 0x0fff0000
+0+104 <[^>]+> 00000000 .word 0x00000000
+0+108 <[^>]+> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+0+10c <[^>]+> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+0+110 <[^>]+> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+0+114 <[^>]+> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+0+118 <[^>]+> ef80 0e34 vmov.i64 d0, #0x0000000000ff0000
+0+11c <[^>]+> ef80 ee34 vmov.i64 d14, #0x0000000000ff0000
+0+120 <[^>]+> efc0 ce34 vmov.i64 d28, #0x0000000000ff0000
+0+124 <[^>]+> efc0 fe34 vmov.i64 d31, #0x0000000000ff0000
+0+128 <[^>]+> ef80 0e39 vmov.i64 d0, #0x00000000ff0000ff
+0+12c <[^>]+> ef80 ee39 vmov.i64 d14, #0x00000000ff0000ff
+0+130 <[^>]+> efc0 ce39 vmov.i64 d28, #0x00000000ff0000ff
+0+134 <[^>]+> efc0 fe39 vmov.i64 d31, #0x00000000ff0000ff
+0+138 <[^>]+> ed9f 0b03 vldr d0, \[pc, #12\] ; 00+148 <[^>]*>
+0+13c <[^>]+> ed9f eb02 vldr d14, \[pc, #8\] ; 00+148 <[^>]*>
+0+140 <[^>]+> eddf cb01 vldr d28, \[pc, #4\] ; 00+148 <[^>]*>
+0+144 <[^>]+> eddf fb00 vldr d31, \[pc\] ; 00+148 <[^>]*>
+0+148 <[^>]+> 00fff000 .word 0x00fff000
+0+14c <[^>]+> 00000000 .word 0x00000000
+0+150 <[^>]+> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+0+154 <[^>]+> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+0+158 <[^>]+> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+0+15c <[^>]+> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+0+160 <[^>]+> ff80 0e30 vmov.i64 d0, #0xff00000000000000
+0+164 <[^>]+> ff80 ee30 vmov.i64 d14, #0xff00000000000000
+0+168 <[^>]+> ffc0 ce30 vmov.i64 d28, #0xff00000000000000
+0+16c <[^>]+> ffc0 fe30 vmov.i64 d31, #0xff00000000000000
+0+170 <[^>]+> ff87 0e3f vmov.i64 d0, #0xffffffffffffffff
+0+174 <[^>]+> ff87 ee3f vmov.i64 d14, #0xffffffffffffffff
+0+178 <[^>]+> ffc7 ce3f vmov.i64 d28, #0xffffffffffffffff
+0+17c <[^>]+> ffc7 fe3f vmov.i64 d31, #0xffffffffffffffff
+0+180 <[^>]+> ed9f 0b03 vldr d0, \[pc, #12\] ; 00+190 <[^>]*>
+0+184 <[^>]+> ed9f eb02 vldr d14, \[pc, #8\] ; 00+190 <[^>]*>
+0+188 <[^>]+> eddf cb01 vldr d28, \[pc, #4\] ; 00+190 <[^>]*>
+0+18c <[^>]+> eddf fb00 vldr d31, \[pc\] ; 00+190 <[^>]*>
+0+190 <[^>]+> 00000000 .word 0x00000000
+0+194 <[^>]+> 0fff0000 .word 0x0fff0000
+0+198 <[^>]+> ef80 0e30 vmov.i64 d0, #0x0000000000000000
+0+19c <[^>]+> ef80 ee30 vmov.i64 d14, #0x0000000000000000
+0+1a0 <[^>]+> efc0 ce30 vmov.i64 d28, #0x0000000000000000
+0+1a4 <[^>]+> efc0 fe30 vmov.i64 d31, #0x0000000000000000
+0+1a8 <[^>]+> ed9f 0b0b vldr d0, \[pc, #44\] ; 00+1d8 <[^>]*>
+0+1ac <[^>]+> ed9f eb0a vldr d14, \[pc, #40\] ; 00+1d8 <[^>]*>
+0+1b0 <[^>]+> eddf cb09 vldr d28, \[pc, #36\] ; 00+1d8 <[^>]*>
+0+1b4 <[^>]+> eddf fb08 vldr d31, \[pc, #32\] ; 00+1d8 <[^>]*>
+0+1b8 <[^>]+> ed9f 0b09 vldr d0, \[pc, #36\] ; 00+1e0 <[^>]*>
+0+1bc <[^>]+> ed9f eb08 vldr d14, \[pc, #32\] ; 00+1e0 <[^>]*>
+0+1c0 <[^>]+> eddf cb07 vldr d28, \[pc, #28\] ; 00+1e0 <[^>]*>
+0+1c4 <[^>]+> eddf fb06 vldr d31, \[pc, #24\] ; 00+1e0 <[^>]*>
+0+1c8 <[^>]+> ed9f 0b05 vldr d0, \[pc, #20\] ; 00+1e0 <[^>]*>
+0+1cc <[^>]+> ed9f eb04 vldr d14, \[pc, #16\] ; 00+1e0 <[^>]*>
+0+1d0 <[^>]+> eddf cb03 vldr d28, \[pc, #12\] ; 00+1e0 <[^>]*>
+0+1d4 <[^>]+> eddf fb02 vldr d31, \[pc, #8\] ; 00+1e0 <[^>]*>
+0+1d8 <[^>]+> 00000000 .word 0x00000000
+0+1dc <[^>]+> 000ff000 .word 0x000ff000
+0+1e0 <[^>]+> f0000000 .word 0xf0000000
+0+1e4 <[^>]+> 0ff00fff .word 0x0ff00fff
diff --git a/gas/testsuite/gas/arm/thumb2_pool.s b/gas/testsuite/gas/arm/thumb2_pool.s
index 844e77e..6488bf7 100644
--- a/gas/testsuite/gas/arm/thumb2_pool.s
+++ b/gas/testsuite/gas/arm/thumb2_pool.s
@@ -1,4 +1,5 @@
.text
+ .fpu neon
.thumb
.syntax unified
.thumb_func
@@ -11,3 +12,45 @@ thumb2_ldr:
ldr.w r5, =0x12345678
ldr r1, =0x12345678
.pool
+
+ .macro vlxr regtype const
+ .irp regindex, 0, 14, 28, 31
+ vldr \regtype\regindex, \const
+ .endr
+ .endm
+ # Thumb-2 support vldr literal pool also.
+ vlxr s "=0"
+ vlxr s "=0xff000000"
+ vlxr s "=-1"
+ vlxr s "=0x0fff0000"
+ .pool
+
+ vlxr s "=0"
+ vlxr s "=0x00ff0000"
+ vlxr s "=0xff00ffff"
+ vlxr s "=0x00fff000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0xca000000"
+ vlxr d "=-1"
+ vlxr d "=0x0fff0000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0x00ff0000"
+ vlxr d "=0xff0000ff"
+ vlxr d "=0x00fff000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0xff00000000000000"
+ vlxr d "=-1"
+ vlxr d "=0x0fff000000000000"
+ .pool
+
+ vlxr d "=0"
+ vlxr d "=0x00ff00000000000"
+ vlxr d "=0xff00ffff0000000"
+ vlxr d "=0xff00ffff0000000"
+ .pool