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RE: [PATCH] Add support for MIPS64r6

From: Andrew Bennett <Andrew dot Bennett at imgtec dot com>
To: Richard Sandiford <rdsandiford at googlemail dot com>
Cc: "binutils at sourceware dot org" <binutils at sourceware dot org>, Rich Fuhler <Rich dot Fuhler at imgtec dot com>, Matthew Fortune <Matthew dot Fortune at imgtec dot com>, "Saeed Ghazanfar" <Saeed dot Ghazanfar at imgtec dot com>
Date: Thu, 19 Jun 2014 16:28:04 +0000
Subject: RE: [PATCH] Add support for MIPS64r6
Authentication-results: sourceware.org; auth=none
References: <0DA23CC379F5F945ACB41CF394B98277575FCF at LEMAIL01 dot le dot imgtec dot org> <871tw55vds dot fsf at talisman dot default> <0DA23CC379F5F945ACB41CF394B9827757AE7E at LEMAIL01 dot le dot imgtec dot org> <87zjikb01y dot fsf at talisman dot default>
> From: Richard Sandiford [mailto:rdsandiford@googlemail.com]
> Sent: 14 May 2014 21:03
> To: Andrew Bennett
> Cc: binutils@sourceware.org; Rich Fuhler; Matthew Fortune; Saeed Ghazanfar
> Subject: Re: [PATCH] Add support for MIPS64r6
> 
> Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
> >> > @@ -1089,7 +1146,8 @@ struct mips_opcode
> >> >     (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) -
> 1)) &
> >> 1
> >> >     is non-zero.  */
> >> >  static const unsigned int mips_isa_table[] =
> >> > -  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf,
> 0x3fff
> >> };
> >> > +  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf,
> 0x3fff,
> >> > +    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x7e63, 0xffff };
> >>
> >> Is it really true that r6 allows everything, given the incompatibility?
> >
> > The problem is that the removed instructions in R6 come from different
> > ISAs.  One approach to solve this is to describe in the membership
> > field the different ISAs an instruction belongs to.  This would
> > require us to create a large amount of different ISA combinations
> > which is hard to manage.  A cleaner approach (and implemented in the
> > patch) is to say that R6 is an extension of R5 and then to deal with
> > the removed instructions by adding instruction exclusions for R6.
> 
> OK, sounds good, thanks.  Please add a comment along those lines.
> 
> >> > @@ -1426,9 +1542,27 @@ print_insn_args (struct disassemble_info *info,
> >> >  		infprintf (is, "$%d,%d", reg, sel);
> >> >  	    }
> >> >  	  else
> >> > -	    print_insn_arg (info, &state, opcode, operand, base_pc,
> >> > -			    mips_extract_operand (operand, insn));
> >> > -	  if (*s == 'm' || *s == '+')
> >> > +	    {
> >> > +	      bfd_vma base_pc = insn_pc;
> >> > +
> >> > +	      /* Adjust the PC relative base so that branch/jump insns use
> >> > +		 the following PC as the base but genuinely PC relative
> >> > +		 operands use the current PC.  */
> >> > +	      if (operand->type == OP_PCREL)
> >> > +		{
> >> > +		  const struct mips_pcrel_operand *pcrel_op;
> >> > +
> >> > +		  pcrel_op = (const struct mips_pcrel_operand *) operand;
> >> > +		  /* The include_isa_bit flag is sufficient to distinguish
> >> > +		     branch/jump from other PC relative operands.  */
> >> > +		  if (pcrel_op->include_isa_bit)
> >> > +		    base_pc += length;
> >> > +		}
> >> > +
> >> > +	      print_insn_arg (info, &state, opcode, operand, base_pc,
> >> > +			      mips_extract_operand (operand, insn));
> >> > +	    }
> >> > +	  if (*s == 'm' || *s == '+' || *s == '-')
> >> >  	    ++s;
> >> >  	  break;
> >> >  	}
> >> > @@ -1494,9 +1628,60 @@ print_insn_mips (bfd_vma memaddr,
> >> >  	      && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
> >> >  	      && (word & op->mask) == op->match)
> >> >  	    {
> >> > +	      if (strcmp (op->name, "bgezc") == 0
> >> > +		  || strcmp (op->name, "bltzc") == 0
> >> > +		  || strcmp (op->name, "bgezalc") == 0
> >> > +		  || strcmp (op->name, "bltzalc") == 0)
> >> > +		{
> >> > +		  if (((word >> 16) & 31) != ((word >> 21) & 31)
> >> > +		      || ((word >> 16) & 31) == 0)
> >> > +		    continue;
> >> > +		}
> >> > +	      else if (strcmp (op->name, "blezalc") == 0
> >> > +		       || strcmp (op->name, "bgtzalc") == 0
> >> > +		       || strcmp (op->name, "blezc") == 0
> >> > +		       || strcmp (op->name, "bgtzc") == 0
> >> > +		       || strcmp (op->name, "beqzalc") == 0
> >> > +		       || strcmp (op->name, "bnezalc") == 0)
> >> > +		{
> >> > +		  if (((word >> 16) & 31) == 0)
> >> > +		    continue;
> >> > +		}
> >> > +	      else if (strcmp (op->name, "bgec") == 0
> >> > +		       || strcmp (op->name, "bltc") == 0
> >> > +		       || strcmp (op->name, "bbec") == 0
> >> > +		       || strcmp (op->name, "bstc") == 0)
> >> > +		{
> >> > +		  if (((word >> 16) & 31) == ((word >> 21) & 31)
> >> > +		      || ((word >> 21) & 31) == 0
> >> > +		      || ((word >> 16) & 31) == 0)
> >> > +		    continue;
> >> > +		}
> >> > +	      else if (strcmp (op->name, "beqc") == 0
> >> > +		       || strcmp (op->name, "bnec") == 0)
> >> > +		{
> >> > +		  if (((word >> 21) & 31) >= ((word >> 16) & 31)
> >> > +		      || ((word >> 21) & 31) == 0)
> >> > +		    continue;
> >> > +		}
> >> > +	      else if (strcmp (op->name, "bovc") == 0
> >> > +		       || strcmp (op->name, "bnvc") == 0)
> >> > +		{
> >> > +		  if (((word >> 21) & 31) < ((word >> 16) & 31))
> >> > +		    continue;
> >> > +		}
> >> > +	      else if (strcmp (op->name, "beqzc") == 0
> >> > +		       || strcmp (op->name, "bnezc") == 0)
> >> > +		{
> >> > +		  if (((word >> 21) & 31) == 0)
> >> > +		    continue;
> >> > +		}
> >>
> >> Looks like this is just reinforcing the restrictions from the OP_*s,
> >> is that right?  If so, I think it would be cleaner to use the
> >> mips_operand information rather than checks for specific instructions.
> >
> > I agree with you that the code could be better here.  The problem is
> > that for some of the R6 instructions the match and mask fields are
> > identical (one example is the bnvc and bnec instructions).  Currently
> > the print_insn_mips function uses the match and mask fields to find
> > the first instruction in the opcode table which matches the
> > instruction to disassemble.  Then it takes each of the operands in
> > turn and checks that they are valid.  This approach will obviously not
> > work when decoding some R6 instructions.  The current fix is to skip
> > over R6 instructions where the operands don't match (which as we said
> > before is not very maintainable).  We could do a more generic fix, but
> > that would require rewriting the print_insn_mips, print_insn_args, and
> > print_insn_arg functions to find an instruction in the opcode table
> > where firstly the match and mask fields match the instruction to
> > disassemble; and secondly all the operand constraints are met.  If
> > this is the case the instruction could then be printed out.
> >
> > I was wondering what you felt would be the best approach here?
> 
> Yeah, rewriting it to treat the new mips_operand type as part of the
> matching criteria sounds better to me.  I realise that might be quite
> invasive, but to be fair, it wasn't easy to predict that this would
> happen when the code was written :-)  I think we should extend what's
> there rather than work around it.

An updated r6 patch is attached that addresses the comments on both this and
the previous email.  I have also added in gas testsuite support for r6 in the
manner described previously.  

The ChangeLog entry is below and the two r6 patches are attached.

Ok to commit?

Regards,


Andrew


/
 	* configure.ac: Add mips*-img-elf* triple.
 	* configure: Regenerate.

bfd/
 	* aoutx.h (NAME (aout, machine_type)): Add mips32r6 and mips64r6.
 	* archures.c (bfd_architecture): Likewise.
 	* bfd-in2.h (bfd_architecture): Likewise.
 	(bfd_reloc_code_real): Add relocs BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
 	BFD_RELOC_MIPS_19_PCREL_S2.
 	* cpu-mips.c (arch_info_struct): Add mips32r6 and mips64r6.
 	* config.bfd: Add mips*-img-elf* triple.
 	* elf32-mips.c: Define relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2
 	R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	* elf64-mips.c: Define partial inplace and non-partial
 	inplace relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
 	R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	* elfn32-mips.c: Define partial inplace and non-partial
 	inplace relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
 	R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	* elfxx-mips.c (MIPSR6_P): New define.
 	(mipsr6_exec_plt_entry): New array.
	(hi16_reloc_p): Add support for R_MIPS_PCHI16.
	(lo16_reloc_p): Add support for R_MIPS_PCLO16.
 	(aligned_pcrel_reloc_p): New function.
 	(mips_elf_relocation_needs_la25_stub): Add support for relocs:
 	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
 	(mips_elf_calculate_relocation): Add support for relocs:
 	R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2,
 	R_MIPS_PCHI16 and R_MIPS_PCLO16. Also allow relocs R_MIPS_PC16 and
 	R_MIPS_GNU_REL16_S2 to support partial inplace.
 	(_bfd_elf_mips_mach): Add support for mips32r6 and mips64r6.
	(mips_elf_add_lo16_rel_addend): Add support for R_MIPS_PCHI16.
 	(_bfd_mips_elf_check_relocs): Add support for relocs: 
	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
 	(_bfd_mips_elf_relocate_section): Add a check for unaligned
 	pc relative relocs.
 	(_bfd_mips_elf_finish_dynamic_symbol): Add support for MIPS r6
 	plt entry.
 	(mips_set_isa_flags): Add support for mips32r6 and mips64r6.
 	(mips_32bit_flags_p): Add supprt for mips32r6.
 	(_bfd_mips_elf_print_private_bfd_data): Add support for mips32r6 
	and mips64r6.
 	* libbfd.h (bfd_reloc_code_real_names): Add entries for
 	BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2,
 	BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2.
 	* reloc.c: Document relocs BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
 	BFD_RELOC_MIPS_19_PCREL_S2.

binutils/
 	* readelf.c (get_machine_flags): Add support for mips32r6 and
 	mips64r6.

elfcpp/
 	* mips.h (E_MIPS_ARCH_32R6, E_MIPS_ARCH_64R6): New enum constants.

gas/
 	* config/tc-mips.c (mips_nan2008): New variable.
	(mips_flag_nan2008): Removed variable.
	(ISA_IS_R6): New define.
 	(ISA_HAS_64BIT_REGS): Add mips64r6.
 	(ISA_HAS_DROR): Likewise.
 	(ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
 	(ISA_HAS_ROR): Likewise.
 	(ISA_HAS_ODD_SINGLE_FPR): Likewise.
 	(ISA_HAS_MXHC1): Likewise.
 	(hilo_interlocks): Likewise.
 	(md_longopts): Likewise.
	(ISA_HAS_LEGACY_NAN): New define.
 	(options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
 	(mips_ase): Add fields mips32_rem_rev, mips64_rem_rev,
 	micromips32_rem_rev and micromips64_rem_rev.
 	(mips_ases): Updated to add which ISA an ASE was removed in.
 	(mips_isa_rev): Add support for mips32r6 and mips64r6.
 	(mips_check_isa_supports_ase): Add support to check if an ASE
 	has been removed in the specified MIPS ISA revision.
 	(validate_mips_insn): Skip '-' character.
	(macro_build): Likewise.
	(mips_check_options): Prevent R6 working with fp32, mips16,
	micromips, or branch relaxation. 
	(file_mips_check_options): Set R6 floating point registers to
	64 bit.  Also deal with the nan2008 option.
 	(limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	(operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV.
 	(match_check_prev_operand): New function.
 	(match_same_rs_rt_operand): New function.
 	(match_operand): Added entries for: OP_SAME_RS_RT and OP_CHECK_PREV.
 	(insns_between): Added case to deal with forbidden slots.
 	(append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
 	and BFD_RELOC_MIPS_26_PCREL_S2
 	(match_insn): Add support for operands -A, -B, +' and +".  Also
 	skip '-' character.
 	(mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
 	(md_parse_option): Add support for mips32r6 and mips64r6.  Also
	update the nan option handling.
 	(md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2. 
 	(mips_force_relocation): Prevent forced relaxation for MIPS r6.
 	(md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	(s_mipsset): Add support for mips32r6 and mips64r6.  
	(s_nan): Update to support the new nan2008 framework.
 	(tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
	(mips_elf_final_processing): Updated to use the new nan2008 flag
	variable.
 	(mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
 	* configure.in: Add support for mips32r6 and mips64r6.
 	* configure: Regenerate.
 	* configure.tgt: Add mips*-img-elf* target triple.
 	* doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
 	options.
	* doc/as.texinfo: Likewise.

gas/testsuite
	* gas/mips/24k-triple-stores-1.s: If testing for r6 prevent 
	non-supported instructions from being tested.
	* gas/mips/24k-triple-stores-2.s: Likewise.
	* gas/mips/24k-triple-stores-3.s: Likewise.
	* gas/mips/24k-triple-stores-6.s: Likewise.
	* gas/mips/add.s: Likewise.
	* gas/mips/beq.s: Likewise.
	* gas/mips/eva.s: Likewise. 
	* gas/mips/ld-zero-3.s: Likewise.
	* gas/mips/mips32-cp2.s: Likewise.
	* gas/mips/mips32.s: Likewise.
	* gas/mips/mips4.s: Likewise.
	* gas/mips/mipsr6@24k-branch-delay-1.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-1.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-2-llsc.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-2.d: New file.  
	* gas/mips/mipsr6@24k-triple-stores-3.d: New file. 
	* gas/mips/mipsr6@24k-triple-stores-6.d: New file.
	* gas/mips/mipsr6@add.d: New file.
	* gas/mips/mipsr6@beq.d: New file.
	* gas/mips/mipsr6@bge.d: New file.
	* gas/mips/mipsr6@bgeu.d: New file. 
	* gas/mips/mipsr6@blt.d: New file.
	* gas/mips/mipsr6@bltu.d: New file.
	* gas/mips/mipsr6@branch-misc-1.d: New file.
	* gas/mips/mipsr6@cache.d: New file.
	* gas/mips/mipsr6@eva.d: New file.
	* gas/mips/mipsr6@jal-svr4pic-noreorder.d: New file.
	* gas/mips/mipsr6@jal-svr4pic.d: New file.
	* gas/mips/mipsr6@ld-zero-3.d: New file.
	* gas/mips/mipsr6@loc-swap-dis.d: New file.
	* gas/mips/mipsr6@mips32-cp2.d: New file.
	* gas/mips/mipsr6@mips32-imm.d: New file. 
	* gas/mips/mipsr6@mips32.d: New file.
	* gas/mips/mipsr6@mips32r2.d: New file.
	* gas/mips/mipsr6@mips4-fp.d: New file.
	* gas/mips/mipsr6@mips4-fp.l: New file.
	* gas/mips/mipsr6@mips4-fp.s: New file.  
	* gas/mips/mipsr6@mips4.d: New file.
	* gas/mips/mipsr6@mips5-fp.d: New file.
	* gas/mips/mipsr6@mips5-fp.l: New file.
	* gas/mips/mipsr6@mips5-fp.s: New file.
	* gas/mips/mipsr6@mips64.d: New file.
	* gas/mips/mipsr6@msa-branch.d: New file.
	* gas/mips/mipsr6@msa.d: New file.
	* gas/mips/mipsr6@pref.d: New file.
	* gas/mips/mipsr6@relax-swap3.d: New file.
	* gas/mips/r6-64-removed.l: New file.
	* gas/mips/r6-64-removed.s: New file.
	* gas/mips/r6-64.d: New file.
	* gas/mips/r6-64.s: New file.
	* gas/mips/r6-removed.l: New file.
	* gas/mips/r6-removed.s: New file.
	* gas/mips/r6.d: New file.
	* gas/mips/r6.s: New file.
	* gas/mips/cache.s: Add r6 instruction varients.
	* gas/mips/mips.exp: Add support for the mips32r6 and mips64r6
	architectures.  Also prevent non r6 supported tests from running.  
	Finally, add in support for running the new r6 tests.
	(run_dump_test_arch): Add support for mipsr6 tests.
	(run_list_test_arch): Add support for using files of the 
	form arch@testname.l . 

include/elf
 	* mips.h: Add relocs: R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
 	R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(E_MIPS_ARCH_32R6): New define.
 	(E_MIPS_ARCH_64R6): New define.

include/opcode
 	* mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT and
 	OP_CHECK_PREV.  Add descriptions for the MIPS R6 instruction 
	arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B, +I, 
	+O, +R, +:, +\, +", +;
	(mips_check_prev_operand): New struct.
 	(INSN2_FORBIDDEN_SLOT): New define.
 	(INSN_ISA32R6): New define.
 	(INSN_ISA64R6): New define.
	(INSN_UPTO32R6): New define.
	(INSN_UPTO64R6): New define.
	(mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
 	(ISA_MIPS32R6): New define.
 	(ISA_MIPS64R6): New define.
 	(CPU_MIPS32R6): New define.
 	(CPU_MIPS64R6): New define.
 	(cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.

ld/
 	* configure.tgt: Add img*-mips-elf* target triple.
 	* ldmain.c (get_emulation): Add support for -mips32r6 and -mips64r6.

ld/testsuite/
 	* ld-mips-elf/mips-elf.exp: Add support for mips*-img-elf* target
 	triple.

opcodes/
 	* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 	mips64r6.
 	(parse_mips_dis_option): Allow MSA and virtualization support for
 	mips64r6.
 	(mips_print_arg_state): Add fields dest_regno and seen_dest.
 	(mips_seen_register): New function.
	(print_insn_arg): 
 	(print_insn_arg): Change return type to be bfd_boolean. 
	Refactored code to use mips_seen_register function.  Add 
	support for OP_SAME_RS_RT, OP_CHECK_PREV.  Changed
	OP_REPEAT_DEST_REG case to print out the register rather than
	aborting.
 	(print_insn_args): Add length argument.  Changed return type to 
	bfd_boolean.  Add code to correctly calculate the instruction 
	address for pc relative instructions.  Return if the call to
	print_insn_arg was successful.
	(DIS_BUF_SIZE): New define.
	(line_dis_buf): New array.
	(line_dis_ptr): New variable.
	(fprintf_dis_buf): New function.
 	(print_insn_mips): Prevent jalx disassembling for r6.  Only output 
	the disassembled instruction if all the arguments are valid.  
	(print_mips16_insn_arg): Changed return type to bfd_boolean. Return
	if the call to print_insn_arg was successful.
	(print_insn_mips16): Only output the disassembled instruction if 
	all the arguments are valid.
	(print_insn_micromips): Likewise.
	* mips-formats.h (PREV_CHECK): New define.
 	* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 	-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 	(RD_pc): New define.
 	(FS): New define.
 	(I37): New define.
 	(I69): New define.
 	(mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 	MIPS R6 instructions from MIPS R2 instructions.
Attachment: r6.tar.gz
Description: r6.tar.gz
Follow-Ups:
- Re: [PATCH] Add support for MIPS64r6
  - From: Richard Sandiford
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