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[PATCH, AArch64] PR17415 error when overflow in relocation R_AARCH64_TLSLE_ADD_TPREL_HI12,*
- From: Jiong Wang <jiong dot wang at arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Wed, 07 Jan 2015 09:32:08 +0000
- Subject: [PATCH, AArch64] PR17415 error when overflow in relocation R_AARCH64_TLSLE_ADD_TPREL_HI12,*
- Authentication-results: sourceware.org; auth=none
aarch64 ld are silently ignore the overflow in R_AARCH64_TLSLE_ADD_TPREL_HI12.
actually there are generic overflow check infrastructure in AArch64 already in
_bfd_aarch64_elf_put_addend. the problem is we haven't enable it for R_AARCH64_TLSLE_ADD_TPREL_HI12.
and the calculation of addend for R_AARCH64_TLSLE_ADD_TPREL_HI12 is wrong in _bfd_aarch64_elf_resolve_relocation.
we shouldn't use "value & 0xfff000" to fetch the high 12 bit value, because this will paper over those overflowed bits.
we should use "value & ~(bfd_vma) 0xfff" to mask off low 12bit, keep all high bits, then pass the result value
to _bfd_aarch64_elf_put_addend, and _bfd_aarch64_elf_put_addend will do the overflow check automatically.
no regression on aarch64 native ld test.
ok for trunk?
bfd/
PR17415
elfnn-aarch64.c (elfNN_aarch64_howto_table): Mark R_AARCH64_TLSLE_ADD_TPREL_HI12 as
complain_overflow_unsigned.
elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Correct the bit mask.
ld/testsuite/
PR17415
ld-aarch64/pr17415.s: Source file for new test.
ld-aarch64/pr17415.d: Expect file for new test.
ld-aarch64/aarch64-elf.exp: Run the new test.
diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
index 4f0e0c6..404273d 100644
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -1038,7 +1038,7 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
12, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
- complain_overflow_dont, /* complain_on_overflow */
+ complain_overflow_unsigned, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
AARCH64_R_STR (TLSLE_ADD_TPREL_HI12), /* name */
FALSE, /* partial_inplace */
diff --git a/bfd/elfxx-aarch64.c b/bfd/elfxx-aarch64.c
index 6ae4adf..f3578bb 100644
--- a/bfd/elfxx-aarch64.c
+++ b/bfd/elfxx-aarch64.c
@@ -450,7 +450,9 @@ _bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type,
value = (value + addend) & (bfd_vma) 0xffff0000;
break;
case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
- value = (value + addend) & (bfd_vma) 0xfff000;
+ /* Mask off low 12bits, keep all other high bits, so that the later
+ generic code could check whehter there is overflow. */
+ value = (value + addend) & ~(bfd_vma) 0xfff;
break;
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp
index a75e070..09c2cd0 100644
--- a/ld/testsuite/ld-aarch64/aarch64-elf.exp
+++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp
@@ -130,6 +130,7 @@ run_dump_test "gc-tls-relocs"
run_dump_test "gc-plt-relocs"
run_dump_test "gc-relocs-257-dyn"
run_dump_test "gc-relocs-257"
+run_dump_test "pr17415"
# ifunc tests
run_dump_test "ifunc-1"
diff --git a/ld/testsuite/ld-aarch64/pr17415.d b/ld/testsuite/ld-aarch64/pr17415.d
new file mode 100644
index 0000000..3f5eb7d
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/pr17415.d
@@ -0,0 +1,6 @@
+#name: TLS offset out of range
+#source: pr17415.s
+#as:
+#ld: -e0
+#error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_TLSLE_ADD_TPREL_HI12 against symbol `i' .*
+
diff --git a/ld/testsuite/ld-aarch64/pr17415.s b/ld/testsuite/ld-aarch64/pr17415.s
new file mode 100644
index 0000000..397bacb
--- /dev/null
+++ b/ld/testsuite/ld-aarch64/pr17415.s
@@ -0,0 +1,43 @@
+ .cpu generic
+ .global ff
+ .section .tbss,"awT",%nobits
+ .align 3
+ .type ff, %object
+ .size ff, 67108864
+ff:
+ .zero 67108864
+ .global i
+ .align 2
+ .type i, %object
+ .size i, 4
+i:
+ .zero 4
+ .text
+ .align 2
+ .global main
+ .type main, %function
+main:
+ sub sp, sp, #16
+ str wzr, [sp,12]
+ b .L2
+.L3:
+ mrs x0, tpidr_el0
+ add x1, x0, #:tprel_hi12:ff
+ add x1, x1, #:tprel_lo12_nc:ff
+ ldrsw x0, [sp,12]
+ mov w2, 7
+ strb w2, [x1,x0]
+ ldr w0, [sp,12]
+ add w0, w0, 1
+ str w0, [sp,12]
+.L2:
+ ldr w0, [sp,12]
+ cmp w0, 999
+ ble .L3
+ mrs x0, tpidr_el0
+ add x0, x0, #:tprel_hi12:i
+ add x0, x0, #:tprel_lo12_nc:i
+ ldr w0, [x0]
+ add sp, sp, 16
+ ret
+ .size main, .-main