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RE: [PATCH] Add XPA ASE and MIPS R5 microMIPS support
- From: Andrew Bennett <Andrew dot Bennett at imgtec dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: "rdsandiford at googlemail dot com" <rdsandiford at googlemail dot com>
- Date: Mon, 9 Mar 2015 08:58:06 +0000
- Subject: RE: [PATCH] Add XPA ASE and MIPS R5 microMIPS support
- Authentication-results: sourceware.org; auth=none
- References: <0DA23CC379F5F945ACB41CF394B9827720F811E1 at LEMAIL01 dot le dot imgtec dot org>
Hi,
It appears I missed off the testsuite changes from my original patch so I have
resubmitted it again with these included.
Regards,
Andrew
gas/
* config/tc-mips.c (mips_ases): Add XPA support for micromips.
gas/testsuite/
* gas/mips/mips.exp: Enable support for micromips for the xpa and r5
tests.
* gas/mips/micromips@xpa.d: New test.
* gas/mips/micromips@r5.d: New test.
opcodes/
* micromips-opc.c (I36): New define.
(XPA): New define.
(micromips_opcodes): Add XPA and eretnc instructions.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index af18430..a1ed610 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1707,7 +1707,7 @@ static const struct mips_ase mips_ases[] = {
{ "xpa", ASE_XPA, 0,
OPTION_XPA, OPTION_NO_XPA,
- 2, 2, -1, -1,
+ 2, 2, 2, 2,
-1 },
};
diff --git a/gas/testsuite/gas/mips/micromips@r5.d b/gas/testsuite/gas/mips/micromips@r5.d
new file mode 100644
index 0000000..ce10398
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@r5.d
@@ -0,0 +1,9 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source: r5.s
+#name: Test MIPS32r5 instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0001f37c eretnc
+ ...
diff --git a/gas/testsuite/gas/mips/micromips@xpa.d b/gas/testsuite/gas/mips/micromips@xpa.d
new file mode 100644
index 0000000..acdec56
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@xpa.d
@@ -0,0 +1,25 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mxpa,cp0-names=mips32r2
+#name: XPA instructions
+#source: xpa.s
+#as: -32 -mxpa
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0041 00f4 mfhc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 0050 00f4 mfhc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 0040 10f4 mfhc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 0040 38f4 mfhc0 v0,\$0,7
+[0-9a-f]+ <[^>]*> 0041 02f4 mthc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 0050 02f4 mthc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 0040 12f4 mthc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 0040 3af4 mthc0 v0,\$0,7
+[0-9a-f]+ <[^>]*> 0041 04f4 mfhgc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 0050 04f4 mfhgc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 0040 14f4 mfhgc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 0040 3cf4 mfhgc0 v0,\$0,7
+[0-9a-f]+ <[^>]*> 0041 06f4 mthgc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 0050 06f4 mthgc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 0040 16f4 mthgc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 0040 3ef4 mthgc0 v0,\$0,7
+ ...
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 34414e1..6c93340 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1240,8 +1240,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "msa-relax" [mips_arch_list_matching mips32r2 !mips32r6]
run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2]
- run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2 !micromips]
- run_dump_test_arches "r5" "-32" [mips_arch_list_matching mips32r5 !micromips]
+ run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2]
+ run_dump_test_arches "r5" "-32" [mips_arch_list_matching mips32r5]
run_dump_test "pcrel-1"
run_dump_test "pcrel-2"
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 66c5418..c595a38 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -253,6 +253,7 @@ decode_micromips_operand (const char *p)
are accepted as 64-bit microMIPS ISA. */
#define I1 INSN_ISA1
#define I3 INSN_ISA3
+#define I36 INSN_ISA32R5
/* MIPS DSP ASE support. */
#define WR_a WR_HILO /* Write DSP accumulators (reuse WR_HILO). */
@@ -279,6 +280,9 @@ decode_micromips_operand (const char *p)
#define MSA ASE_MSA
#define MSA64 ASE_MSA64
+/* eXtended Physical Address (XPA) support. */
+#define XPA ASE_XPA
+
const struct mips_opcode micromips_opcodes[] =
{
/* These instructions appear first so that the disassembler will find
@@ -682,6 +686,7 @@ const struct mips_opcode micromips_opcodes[] =
{"ei", "", 0x0000577c, 0xffffffff, WR_C0, 0, I1, 0, 0 },
{"ei", "s", 0x0000577c, 0xffe0ffff, WR_1|WR_C0, 0, I1, 0, 0 },
{"eret", "", 0x0000f37c, 0xffffffff, NODS, 0, I1, 0, 0 },
+{"eretnc", "", 0x0001f37c, 0xffffffff, NODS, 0, I36, 0, 0 },
{"ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 },
{"floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
@@ -826,6 +831,10 @@ const struct mips_opcode micromips_opcodes[] =
{"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
{"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT, 0 },
{"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT, 0 },
+{"mfhc0", "t,G", 0x000000f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPA, 0 },
+{"mfhc0", "t,G,H", 0x000000f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPA, 0 },
+{"mfhgc0", "t,G", 0x000004f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT|XPA, 0 },
+{"mfhgc0", "t,G,H", 0x000004f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT|XPA, 0 },
{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 },
{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 },
{"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
@@ -872,6 +881,10 @@ const struct mips_opcode micromips_opcodes[] =
{"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
{"mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 },
{"mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 },
+{"mthc0", "t,G", 0x000002f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 },
+{"mthc0", "t,G,H", 0x000002f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 },
+{"mthgc0", "t,G", 0x000006f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT|XPA, 0 },
+{"mthgc0", "t,G,H", 0x000006f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT|XPA, 0 },
{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
{"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },