RE: [PATCH] MIPS: Fix constraint issues with the R6 beqc and bnec instructions

[Andrew Bennett <Andrew dot Bennett at imgtec dot com>]

> I have committed this, and also added a testcase that checks the encoding
> constraints for all the
> compact conditional branch instructions.

For completeness the committed patch is shown below.

Regards,


Andrew

    
    opcodes/
    	* mips-opc.c (decode_mips_operand): Fix constraint issues
    	with u and y operands.
    
    gas/testsuite/
    	* gas/mips/mips.exp: Added branch constraints testcase.
    	* gas/mips/r6-branch-constraints.s: New test.
    	* gas/mips/r6-branch-constraints.l: New test.


diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 34414e1..11c9b05 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1454,4 +1454,6 @@ if { [istarget mips*-*-vxworks*] } {
     }
     run_list_test_arches "r6-removed"	"-32" [mips_arch_list_matching mips32r6]
     run_list_test_arches "r6-64-removed"	[mips_arch_list_matching mips64r6]
+
+    run_list_test_arches "r6-branch-constraints"	[mips_arch_list_matching mips32r6]
 }
diff --git a/gas/testsuite/gas/mips/r6-branch-constraints.l b/gas/testsuite/gas/mips/r6-branch-constraints.l
new file mode 100644
index 0000000..819a09a
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-branch-constraints.l
@@ -0,0 +1,25 @@
+.*: Assembler messages:
+.*:2: Error: invalid operands `blezc \$0,.'
+.*:3: Error: the source register must not be \$0 `bgezc \$0,.'
+.*:4: Error: invalid operands `bgtzc \$0,.'
+.*:5: Error: the source register must not be \$0 `bltzc \$0,.'
+.*:6: Error: invalid operands `beqzc \$0,.'
+.*:7: Error: invalid operands `bnezc \$0,.'
+.*:8: Error: invalid operands `bgec \$0,\$2,.'
+.*:9: Error: invalid operands `bgec \$2,\$0,.'
+.*:10: Error: invalid operands `bgec \$2,\$2,.'
+.*:11: Error: invalid operands `bgeuc \$0,\$2,.'
+.*:12: Error: invalid operands `bgeuc \$2,\$0,.'
+.*:13: Error: invalid operands `bgeuc \$2,\$2,.'
+.*:14: Error: invalid operands `bltc \$0,\$2,.'
+.*:15: Error: invalid operands `bltc \$2,\$0,.'
+.*:16: Error: invalid operands `bltc \$2,\$2,.'
+.*:17: Error: invalid operands `bltuc \$0,\$2,.'
+.*:18: Error: invalid operands `bltuc \$2,\$0,.'
+.*:19: Error: invalid operands `bltuc \$2,\$2,.'
+.*:20: Error: invalid operands `beqc \$0,\$2,.'
+.*:21: Error: invalid operands `beqc \$2,\$0,.'
+.*:22: Error: invalid operands `beqc \$2,\$2,.'
+.*:23: Error: invalid operands `bnec \$0,\$2,.'
+.*:24: Error: invalid operands `bnec \$2,\$0,.'
+.*:25: Error: invalid operands `bnec \$2,\$2,.'
diff --git a/gas/testsuite/gas/mips/r6-branch-constraints.s b/gas/testsuite/gas/mips/r6-branch-constraints.s
new file mode 100644
index 0000000..62ca893
--- /dev/null
+++ b/gas/testsuite/gas/mips/r6-branch-constraints.s
@@ -0,0 +1,25 @@
+	.text
+	blezc	    $0,.
+	bgezc	    $0,.
+	bgtzc	    $0,.
+	bltzc	    $0,.
+	beqzc	    $0,.
+	bnezc	    $0,.
+	bgec	    $0,$2,.
+	bgec	    $2,$0,.
+	bgec	    $2,$2,.
+	bgeuc	    $0,$2,.
+	bgeuc	    $2,$0,.
+	bgeuc	    $2,$2,.
+	bltc	    $0,$2,.
+	bltc	    $2,$0,.
+	bltc	    $2,$2,.
+	bltuc	    $0,$2,.
+	bltuc	    $2,$0,.
+	bltuc	    $2,$2,.
+	beqc	    $0,$2,.
+	beqc	    $2,$0,.
+	beqc	    $2,$2,.
+	bnec	    $0,$2,.
+	bnec	    $2,$0,.
+	bnec	    $2,$2,.
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index f43f9f5..a0b0e26 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -48,11 +48,11 @@ decode_mips_operand (const char *p)
 	case 'd': SPECIAL (0, 0, REPEAT_DEST_REG);
 	case 's': SPECIAL (5, 21, NON_ZERO_REG);
 	case 't': SPECIAL (5, 16, NON_ZERO_REG);
-	case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, TRUE);
+	case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, FALSE);
 	case 'v': PREV_CHECK (5, 16, TRUE, TRUE, FALSE, FALSE);
 	case 'w': PREV_CHECK (5, 16, FALSE, TRUE, TRUE, TRUE);
 	case 'x': PREV_CHECK (5, 21, TRUE, FALSE, FALSE, TRUE);
-	case 'y': PREV_CHECK (5, 21, FALSE, TRUE, TRUE, FALSE);
+	case 'y': PREV_CHECK (5, 21, FALSE, TRUE, FALSE, FALSE);
 	case 'A': PCREL (19, 0, TRUE, 2, 2, FALSE, FALSE);
 	case 'B': PCREL (18, 0, TRUE, 3, 3, FALSE, FALSE);
 	}