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Re: [PATCH v2] ARM: Add AArch32 support for gold linker.
- From: HÃn ShÄn (ææ) <shenhan at google dot com>
- To: HC Yen <hc dot yen at mediatek dot com>, Cary Coutant <ccoutant at google dot com>, Luis Lozano <llozano at google dot com>
- Cc: binutils <binutils at sourceware dot org>, Han Shen <shenhan at chromium dot org>, srv_heupstream at mediatek dot com
- Date: Thu, 26 Mar 2015 20:55:03 -0700
- Subject: Re: [PATCH v2] ARM: Add AArch32 support for gold linker.
- Authentication-results: sourceware.org; auth=none
- References: <1427347538-890-1-git-send-email-hc dot yen at mediatek dot com>
Hi Cary, we are building system using aarch32, and we need this to use
Gold as the default linker.
We tested this by building the whole aarch32 system using gold from
scratch, and the system boots successfully.
Is this patch OK for trunk?
Thanks,
Han
On Wed, Mar 25, 2015 at 10:25 PM, HC Yen <hc.yen@mediatek.com> wrote:
> elfcpp:
> * arm.h: Add TAG_CPU_ARCH_V8 in Tag_CPU_arch EABI attribute.
>
> gold:
> * arm.cc: Add V8 arch combine table.
> ---
> elfcpp/arm.h | 3 ++-
> gold/arm.cc | 23 ++++++++++++++++++++++-
> 2 files changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/elfcpp/arm.h b/elfcpp/arm.h
> index c9cb753..14109b9 100644
> --- a/elfcpp/arm.h
> +++ b/elfcpp/arm.h
> @@ -248,7 +248,8 @@ enum
> TAG_CPU_ARCH_V6_M,
> TAG_CPU_ARCH_V6S_M,
> TAG_CPU_ARCH_V7E_M,
> - MAX_TAG_CPU_ARCH = TAG_CPU_ARCH_V7E_M,
> + TAG_CPU_ARCH_V8,
> + MAX_TAG_CPU_ARCH = TAG_CPU_ARCH_V8,
> // Pseudo-architecture to allow objects to be compatible with the subset of
> // armv4t and armv6-m. This value should never be stored in object files.
> TAG_CPU_ARCH_V4T_PLUS_V6_M = (MAX_TAG_CPU_ARCH + 1)
> diff --git a/gold/arm.cc b/gold/arm.cc
> index f1d4fe9..5f6db41 100644
> --- a/gold/arm.cc
> +++ b/gold/arm.cc
> @@ -10759,6 +10759,24 @@ Target_arm<big_endian>::tag_cpu_arch_combine(
> T(V7E_M), // V6S_M.
> T(V7E_M) // V7E_M.
> };
> + static const int v8[] =
> + {
> + T(V8), // PRE_V4.
> + T(V8), // V4.
> + T(V8), // V4T.
> + T(V8), // V5T.
> + T(V8), // V5TE.
> + T(V8), // V5TEJ.
> + T(V8), // V6.
> + T(V8), // V6KZ.
> + T(V8), // V6T2.
> + T(V8), // V6K.
> + T(V8), // V7.
> + T(V8), // V6_M.
> + T(V8), // V6S_M.
> + T(V8), // V7E_M.
> + T(V8) // V8.
> + };
> static const int v4t_plus_v6_m[] =
> {
> -1, // PRE_V4.
> @@ -10775,6 +10793,7 @@ Target_arm<big_endian>::tag_cpu_arch_combine(
> T(V6_M), // V6_M.
> T(V6S_M), // V6S_M.
> T(V7E_M), // V7E_M.
> + T(V8), // V8.
> T(V4T_PLUS_V6_M) // V4T plus V6_M.
> };
> static const int* comb[] =
> @@ -10785,6 +10804,7 @@ Target_arm<big_endian>::tag_cpu_arch_combine(
> v6_m,
> v6s_m,
> v7e_m,
> + v8,
> // Pseudo-architecture.
> v4t_plus_v6_m
> };
> @@ -10882,7 +10902,8 @@ Target_arm<big_endian>::tag_cpu_name_value(unsigned int value)
> "ARM v7",
> "ARM v6-M",
> "ARM v6S-M",
> - "ARM v7E-M"
> + "ARM v7E-M",
> + "ARM v8"
> };
> const size_t name_table_size = sizeof(name_table) / sizeof(name_table[0]);
>
> --
> 1.7.9.5
>
--
Han Shen | Software Engineer | shenhan@google.com | +1-650-440-3330