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Certain conversion operations as well as vfpclassp{d,s} are ambiguous
when the input operand is in memory. That ambiguity, however, doesn't
apply when using broadcasts (the destination operand size can be
induced from the broadcast specifier).
gas/
2015-04-16 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_mem_size): Also allow no size
specification when broadcasting.
gas/testsuite/
2015-04-16 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512dq.s: Drop 'z' suffix from vfpclassp{d,s} in
some AT&T and all Intel cases.
* gas/i386/x86-64-avx512dq.s: Likewise.
* gas/i386/avx512dq_vl.s: Drop 'x' and 'y' suffixes from
vcvt{,u}qq2ps and vfpclassp{d,s} in some AT&T and all Intel
cases.
* gas/i386/x86-64-avx512dq_vl.s: Likewise.
* gas/i386/avx512f_vl.s: Drop 'x' and 'y' suffixes from
vcvt{,t}pd2{,u}dq and vcvtpd2ps in some AT&T and all Intel
cases.
* gas/i386/x86-64-avx512f_vl.s: Likewise.
--- 2015-04-16/gas/config/tc-i386.c
+++ 2015-04-16/gas/config/tc-i386.c
@@ -1686,6 +1686,7 @@ match_mem_size (const insn_template *t,
{
return (match_reg_size (t, j)
&& !((i.types[j].bitfield.unspecified
+ && !i.broadcast
&& !t->operand_types[j].bitfield.unspecified)
|| (i.types[j].bitfield.fword
&& !t->operand_types[j].bitfield.fword)
--- 2015-04-16/gas/testsuite/gas/i386/avx512dq.s
+++ 2015-04-16/gas/testsuite/gas/i386/avx512dq.s
@@ -201,7 +201,7 @@ _start:
vfpclasspd $123, %zmm6, %k5 # AVX512DQ
vfpclasspdz $123, (%ecx), %k5 # AVX512DQ
vfpclasspdz $123, -123456(%esp,%esi,8), %k5 # AVX512DQ
- vfpclasspdz $123, (%eax){1to8}, %k5 # AVX512DQ
+ vfpclasspd $123, (%eax){1to8}, %k5 # AVX512DQ
vfpclasspdz $123, 8128(%edx), %k5 # AVX512DQ Disp8
vfpclasspdz $123, 8192(%edx), %k5 # AVX512DQ
vfpclasspdz $123, -8192(%edx), %k5 # AVX512DQ Disp8
@@ -215,7 +215,7 @@ _start:
vfpclassps $123, %zmm6, %k5 # AVX512DQ
vfpclasspsz $123, (%ecx), %k5 # AVX512DQ
vfpclasspsz $123, -123456(%esp,%esi,8), %k5 # AVX512DQ
- vfpclasspsz $123, (%eax){1to16}, %k5 # AVX512DQ
+ vfpclassps $123, (%eax){1to16}, %k5 # AVX512DQ
vfpclasspsz $123, 8128(%edx), %k5 # AVX512DQ Disp8
vfpclasspsz $123, 8192(%edx), %k5 # AVX512DQ
vfpclasspsz $123, -8192(%edx), %k5 # AVX512DQ Disp8
@@ -841,29 +841,29 @@ _start:
vfpclasspd k5, zmm6, 123 # AVX512DQ
vfpclasspd k5, ZMMWORD PTR [ecx], 123 # AVX512DQ
vfpclasspd k5, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512DQ
- vfpclasspdz k5, [eax]{1to8}, 123 # AVX512DQ
+ vfpclasspd k5, [eax]{1to8}, 123 # AVX512DQ
vfpclasspd k5, ZMMWORD PTR [edx+8128], 123 # AVX512DQ Disp8
vfpclasspd k5, ZMMWORD PTR [edx+8192], 123 # AVX512DQ
vfpclasspd k5, ZMMWORD PTR [edx-8192], 123 # AVX512DQ Disp8
vfpclasspd k5, ZMMWORD PTR [edx-8256], 123 # AVX512DQ
- vfpclasspdz k5, [edx+1016]{1to8}, 123 # AVX512DQ Disp8
- vfpclasspdz k5, [edx+1024]{1to8}, 123 # AVX512DQ
- vfpclasspdz k5, [edx-1024]{1to8}, 123 # AVX512DQ Disp8
- vfpclasspdz k5, [edx-1032]{1to8}, 123 # AVX512DQ
+ vfpclasspd k5, QWORD PTR [edx+1016]{1to8}, 123 # AVX512DQ Disp8
+ vfpclasspd k5, QWORD PTR [edx+1024]{1to8}, 123 # AVX512DQ
+ vfpclasspd k5, QWORD PTR [edx-1024]{1to8}, 123 # AVX512DQ Disp8
+ vfpclasspd k5, QWORD PTR [edx-1032]{1to8}, 123 # AVX512DQ
vfpclassps k5, zmm6, 0xab # AVX512DQ
vfpclassps k5{k7}, zmm6, 0xab # AVX512DQ
vfpclassps k5, zmm6, 123 # AVX512DQ
vfpclassps k5, ZMMWORD PTR [ecx], 123 # AVX512DQ
vfpclassps k5, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512DQ
- vfpclasspsz k5, [eax]{1to16}, 123 # AVX512DQ
+ vfpclassps k5, [eax]{1to16}, 123 # AVX512DQ
vfpclassps k5, ZMMWORD PTR [edx+8128], 123 # AVX512DQ Disp8
vfpclassps k5, ZMMWORD PTR [edx+8192], 123 # AVX512DQ
vfpclassps k5, ZMMWORD PTR [edx-8192], 123 # AVX512DQ Disp8
vfpclassps k5, ZMMWORD PTR [edx-8256], 123 # AVX512DQ
- vfpclasspsz k5, [edx+508]{1to16}, 123 # AVX512DQ Disp8
- vfpclasspsz k5, [edx+512]{1to16}, 123 # AVX512DQ
- vfpclasspsz k5, [edx-512]{1to16}, 123 # AVX512DQ Disp8
- vfpclasspsz k5, [edx-516]{1to16}, 123 # AVX512DQ
+ vfpclassps k5, DWORD PTR [edx+508]{1to16}, 123 # AVX512DQ Disp8
+ vfpclassps k5, DWORD PTR [edx+512]{1to16}, 123 # AVX512DQ
+ vfpclassps k5, DWORD PTR [edx-512]{1to16}, 123 # AVX512DQ Disp8
+ vfpclassps k5, DWORD PTR [edx-516]{1to16}, 123 # AVX512DQ
vfpclasssd k5{k7}, xmm6, 0xab # AVX512DQ
vfpclasssd k5{k7}, xmm6, 123 # AVX512DQ
vfpclasssd k5{k7}, QWORD PTR [ecx], 123 # AVX512DQ
--- 2015-04-16/gas/testsuite/gas/i386/avx512dq_vl.s
+++ 2015-04-16/gas/testsuite/gas/i386/avx512dq_vl.s
@@ -159,7 +159,7 @@ _start:
vcvtqq2ps %xmm5, %xmm6{%k7}{z} # AVX512{DQ,VL}
vcvtqq2psx (%ecx), %xmm6{%k7} # AVX512{DQ,VL}
vcvtqq2psx -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{DQ,VL}
- vcvtqq2psx (%eax){1to2}, %xmm6{%k7} # AVX512{DQ,VL}
+ vcvtqq2ps (%eax){1to2}, %xmm6{%k7} # AVX512{DQ,VL}
vcvtqq2psx 2032(%edx), %xmm6{%k7} # AVX512{DQ,VL} Disp8
vcvtqq2psx 2048(%edx), %xmm6{%k7} # AVX512{DQ,VL}
vcvtqq2psx -2048(%edx), %xmm6{%k7} # AVX512{DQ,VL} Disp8
@@ -172,7 +172,7 @@ _start:
vcvtqq2ps %ymm5, %xmm6{%k7}{z} # AVX512{DQ,VL}
vcvtqq2psy (%ecx), %xmm6{%k7} # AVX512{DQ,VL}
vcvtqq2psy -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{DQ,VL}
- vcvtqq2psy (%eax){1to4}, %xmm6{%k7} # AVX512{DQ,VL}
+ vcvtqq2ps (%eax){1to4}, %xmm6{%k7} # AVX512{DQ,VL}
vcvtqq2psy 4064(%edx), %xmm6{%k7} # AVX512{DQ,VL} Disp8
vcvtqq2psy 4096(%edx), %xmm6{%k7} # AVX512{DQ,VL}
vcvtqq2psy -4096(%edx), %xmm6{%k7} # AVX512{DQ,VL} Disp8
@@ -211,7 +211,7 @@ _start:
vcvtuqq2ps %xmm5, %xmm6{%k7}{z} # AVX512{DQ,VL}
vcvtuqq2psx (%ecx), %xmm6{%k7} # AVX512{DQ,VL}
vcvtuqq2psx -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{DQ,VL}
- vcvtuqq2psx (%eax){1to2}, %xmm6{%k7} # AVX512{DQ,VL}
+ vcvtuqq2ps (%eax){1to2}, %xmm6{%k7} # AVX512{DQ,VL}
vcvtuqq2psx 2032(%edx), %xmm6{%k7} # AVX512{DQ,VL} Disp8
vcvtuqq2psx 2048(%edx), %xmm6{%k7} # AVX512{DQ,VL}
vcvtuqq2psx -2048(%edx), %xmm6{%k7} # AVX512{DQ,VL} Disp8
@@ -224,7 +224,7 @@ _start:
vcvtuqq2ps %ymm5, %xmm6{%k7}{z} # AVX512{DQ,VL}
vcvtuqq2psy (%ecx), %xmm6{%k7} # AVX512{DQ,VL}
vcvtuqq2psy -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{DQ,VL}
- vcvtuqq2psy (%eax){1to4}, %xmm6{%k7} # AVX512{DQ,VL}
+ vcvtuqq2ps (%eax){1to4}, %xmm6{%k7} # AVX512{DQ,VL}
vcvtuqq2psy 4064(%edx), %xmm6{%k7} # AVX512{DQ,VL} Disp8
vcvtuqq2psy 4096(%edx), %xmm6{%k7} # AVX512{DQ,VL}
vcvtuqq2psy -4096(%edx), %xmm6{%k7} # AVX512{DQ,VL} Disp8
@@ -243,7 +243,7 @@ _start:
vfpclasspd $123, %xmm6, %k5{%k7} # AVX512{DQ,VL}
vfpclasspdx $123, (%ecx), %k5{%k7} # AVX512{DQ,VL}
vfpclasspdx $123, -123456(%esp,%esi,8), %k5{%k7} # AVX512{DQ,VL}
- vfpclasspdx $123, (%eax){1to2}, %k5{%k7} # AVX512{DQ,VL}
+ vfpclasspd $123, (%eax){1to2}, %k5{%k7} # AVX512{DQ,VL}
vfpclasspdx $123, 2032(%edx), %k5{%k7} # AVX512{DQ,VL} Disp8
vfpclasspdx $123, 2048(%edx), %k5{%k7} # AVX512{DQ,VL}
vfpclasspdx $123, -2048(%edx), %k5{%k7} # AVX512{DQ,VL} Disp8
@@ -256,7 +256,7 @@ _start:
vfpclasspd $123, %ymm6, %k5{%k7} # AVX512{DQ,VL}
vfpclasspdy $123, (%ecx), %k5{%k7} # AVX512{DQ,VL}
vfpclasspdy $123, -123456(%esp,%esi,8), %k5{%k7} # AVX512{DQ,VL}
- vfpclasspdy $123, (%eax){1to4}, %k5{%k7} # AVX512{DQ,VL}
+ vfpclasspd $123, (%eax){1to4}, %k5{%k7} # AVX512{DQ,VL}
vfpclasspdy $123, 4064(%edx), %k5{%k7} # AVX512{DQ,VL} Disp8
vfpclasspdy $123, 4096(%edx), %k5{%k7} # AVX512{DQ,VL}
vfpclasspdy $123, -4096(%edx), %k5{%k7} # AVX512{DQ,VL} Disp8
@@ -269,7 +269,7 @@ _start:
vfpclassps $123, %xmm6, %k5{%k7} # AVX512{DQ,VL}
vfpclasspsx $123, (%ecx), %k5{%k7} # AVX512{DQ,VL}
vfpclasspsx $123, -123456(%esp,%esi,8), %k5{%k7} # AVX512{DQ,VL}
- vfpclasspsx $123, (%eax){1to4}, %k5{%k7} # AVX512{DQ,VL}
+ vfpclassps $123, (%eax){1to4}, %k5{%k7} # AVX512{DQ,VL}
vfpclasspsx $123, 2032(%edx), %k5{%k7} # AVX512{DQ,VL} Disp8
vfpclasspsx $123, 2048(%edx), %k5{%k7} # AVX512{DQ,VL}
vfpclasspsx $123, -2048(%edx), %k5{%k7} # AVX512{DQ,VL} Disp8
@@ -282,7 +282,7 @@ _start:
vfpclassps $123, %ymm6, %k5{%k7} # AVX512{DQ,VL}
vfpclasspsy $123, (%ecx), %k5{%k7} # AVX512{DQ,VL}
vfpclasspsy $123, -123456(%esp,%esi,8), %k5{%k7} # AVX512{DQ,VL}
- vfpclasspsy $123, (%eax){1to8}, %k5{%k7} # AVX512{DQ,VL}
+ vfpclassps $123, (%eax){1to8}, %k5{%k7} # AVX512{DQ,VL}
vfpclasspsy $123, 4064(%edx), %k5{%k7} # AVX512{DQ,VL} Disp8
vfpclasspsy $123, 4096(%edx), %k5{%k7} # AVX512{DQ,VL}
vfpclasspsy $123, -4096(%edx), %k5{%k7} # AVX512{DQ,VL} Disp8
@@ -955,28 +955,28 @@ _start:
vcvtqq2ps xmm6{k7}{z}, xmm5 # AVX512{DQ,VL}
vcvtqq2ps xmm6{k7}, XMMWORD PTR [ecx] # AVX512{DQ,VL}
vcvtqq2ps xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{DQ,VL}
- vcvtqq2psx xmm6{k7}, [eax]{1to2} # AVX512{DQ,VL}
+ vcvtqq2ps xmm6{k7}, [eax]{1to2} # AVX512{DQ,VL}
vcvtqq2ps xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{DQ,VL} Disp8
vcvtqq2ps xmm6{k7}, XMMWORD PTR [edx+2048] # AVX512{DQ,VL}
vcvtqq2ps xmm6{k7}, XMMWORD PTR [edx-2048] # AVX512{DQ,VL} Disp8
vcvtqq2ps xmm6{k7}, XMMWORD PTR [edx-2064] # AVX512{DQ,VL}
- vcvtqq2psx xmm6{k7}, [edx+1016]{1to2} # AVX512{DQ,VL} Disp8
- vcvtqq2psx xmm6{k7}, [edx+1024]{1to2} # AVX512{DQ,VL}
- vcvtqq2psx xmm6{k7}, [edx-1024]{1to2} # AVX512{DQ,VL} Disp8
- vcvtqq2psx xmm6{k7}, [edx-1032]{1to2} # AVX512{DQ,VL}
+ vcvtqq2ps xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{DQ,VL} Disp8
+ vcvtqq2ps xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{DQ,VL}
+ vcvtqq2ps xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{DQ,VL} Disp8
+ vcvtqq2ps xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{DQ,VL}
vcvtqq2ps xmm6{k7}, ymm5 # AVX512{DQ,VL}
vcvtqq2ps xmm6{k7}{z}, ymm5 # AVX512{DQ,VL}
vcvtqq2ps xmm6{k7}, YMMWORD PTR [ecx] # AVX512{DQ,VL}
vcvtqq2ps xmm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{DQ,VL}
- vcvtqq2psy xmm6{k7}, [eax]{1to4} # AVX512{DQ,VL}
+ vcvtqq2ps xmm6{k7}, [eax]{1to4} # AVX512{DQ,VL}
vcvtqq2ps xmm6{k7}, YMMWORD PTR [edx+4064] # AVX512{DQ,VL} Disp8
vcvtqq2ps xmm6{k7}, YMMWORD PTR [edx+4096] # AVX512{DQ,VL}
vcvtqq2ps xmm6{k7}, YMMWORD PTR [edx-4096] # AVX512{DQ,VL} Disp8
vcvtqq2ps xmm6{k7}, YMMWORD PTR [edx-4128] # AVX512{DQ,VL}
- vcvtqq2psy xmm6{k7}, [edx+1016]{1to4} # AVX512{DQ,VL} Disp8
- vcvtqq2psy xmm6{k7}, [edx+1024]{1to4} # AVX512{DQ,VL}
- vcvtqq2psy xmm6{k7}, [edx-1024]{1to4} # AVX512{DQ,VL} Disp8
- vcvtqq2psy xmm6{k7}, [edx-1032]{1to4} # AVX512{DQ,VL}
+ vcvtqq2ps xmm6{k7}, QWORD PTR [edx+1016]{1to4} # AVX512{DQ,VL} Disp8
+ vcvtqq2ps xmm6{k7}, QWORD PTR [edx+1024]{1to4} # AVX512{DQ,VL}
+ vcvtqq2ps xmm6{k7}, QWORD PTR [edx-1024]{1to4} # AVX512{DQ,VL} Disp8
+ vcvtqq2ps xmm6{k7}, QWORD PTR [edx-1032]{1to4} # AVX512{DQ,VL}
vcvtuqq2pd xmm6{k7}, xmm5 # AVX512{DQ,VL}
vcvtuqq2pd xmm6{k7}{z}, xmm5 # AVX512{DQ,VL}
vcvtuqq2pd xmm6{k7}, XMMWORD PTR [ecx] # AVX512{DQ,VL}
@@ -1007,28 +1007,28 @@ _start:
vcvtuqq2ps xmm6{k7}{z}, xmm5 # AVX512{DQ,VL}
vcvtuqq2ps xmm6{k7}, XMMWORD PTR [ecx] # AVX512{DQ,VL}
vcvtuqq2ps xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{DQ,VL}
- vcvtuqq2psx xmm6{k7}, [eax]{1to2} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm6{k7}, [eax]{1to2} # AVX512{DQ,VL}
vcvtuqq2ps xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{DQ,VL} Disp8
vcvtuqq2ps xmm6{k7}, XMMWORD PTR [edx+2048] # AVX512{DQ,VL}
vcvtuqq2ps xmm6{k7}, XMMWORD PTR [edx-2048] # AVX512{DQ,VL} Disp8
vcvtuqq2ps xmm6{k7}, XMMWORD PTR [edx-2064] # AVX512{DQ,VL}
- vcvtuqq2psx xmm6{k7}, [edx+1016]{1to2} # AVX512{DQ,VL} Disp8
- vcvtuqq2psx xmm6{k7}, [edx+1024]{1to2} # AVX512{DQ,VL}
- vcvtuqq2psx xmm6{k7}, [edx-1024]{1to2} # AVX512{DQ,VL} Disp8
- vcvtuqq2psx xmm6{k7}, [edx-1032]{1to2} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{DQ,VL} Disp8
+ vcvtuqq2ps xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{DQ,VL} Disp8
+ vcvtuqq2ps xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{DQ,VL}
vcvtuqq2ps xmm6{k7}, ymm5 # AVX512{DQ,VL}
vcvtuqq2ps xmm6{k7}{z}, ymm5 # AVX512{DQ,VL}
vcvtuqq2ps xmm6{k7}, YMMWORD PTR [ecx] # AVX512{DQ,VL}
vcvtuqq2ps xmm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{DQ,VL}
- vcvtuqq2psy xmm6{k7}, [eax]{1to4} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm6{k7}, [eax]{1to4} # AVX512{DQ,VL}
vcvtuqq2ps xmm6{k7}, YMMWORD PTR [edx+4064] # AVX512{DQ,VL} Disp8
vcvtuqq2ps xmm6{k7}, YMMWORD PTR [edx+4096] # AVX512{DQ,VL}
vcvtuqq2ps xmm6{k7}, YMMWORD PTR [edx-4096] # AVX512{DQ,VL} Disp8
vcvtuqq2ps xmm6{k7}, YMMWORD PTR [edx-4128] # AVX512{DQ,VL}
- vcvtuqq2psy xmm6{k7}, [edx+1016]{1to4} # AVX512{DQ,VL} Disp8
- vcvtuqq2psy xmm6{k7}, [edx+1024]{1to4} # AVX512{DQ,VL}
- vcvtuqq2psy xmm6{k7}, [edx-1024]{1to4} # AVX512{DQ,VL} Disp8
- vcvtuqq2psy xmm6{k7}, [edx-1032]{1to4} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm6{k7}, QWORD PTR [edx+1016]{1to4} # AVX512{DQ,VL} Disp8
+ vcvtuqq2ps xmm6{k7}, QWORD PTR [edx+1024]{1to4} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm6{k7}, QWORD PTR [edx-1024]{1to4} # AVX512{DQ,VL} Disp8
+ vcvtuqq2ps xmm6{k7}, QWORD PTR [edx-1032]{1to4} # AVX512{DQ,VL}
vextractf64x2 xmm6{k7}, ymm5, 0xab # AVX512{DQ,VL}
vextractf64x2 xmm6{k7}{z}, ymm5, 0xab # AVX512{DQ,VL}
vextractf64x2 xmm6{k7}, ymm5, 123 # AVX512{DQ,VL}
@@ -1039,54 +1039,54 @@ _start:
vfpclasspd k5{k7}, xmm6, 123 # AVX512{DQ,VL}
vfpclasspd k5{k7}, XMMWORD PTR [ecx], 123 # AVX512{DQ,VL}
vfpclasspd k5{k7}, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512{DQ,VL}
- vfpclasspdx k5{k7}, [eax]{1to2}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5{k7}, [eax]{1to2}, 123 # AVX512{DQ,VL}
vfpclasspd k5{k7}, XMMWORD PTR [edx+2032], 123 # AVX512{DQ,VL} Disp8
vfpclasspd k5{k7}, XMMWORD PTR [edx+2048], 123 # AVX512{DQ,VL}
vfpclasspd k5{k7}, XMMWORD PTR [edx-2048], 123 # AVX512{DQ,VL} Disp8
vfpclasspd k5{k7}, XMMWORD PTR [edx-2064], 123 # AVX512{DQ,VL}
- vfpclasspdx k5{k7}, [edx+1016]{1to2}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspdx k5{k7}, [edx+1024]{1to2}, 123 # AVX512{DQ,VL}
- vfpclasspdx k5{k7}, [edx-1024]{1to2}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspdx k5{k7}, [edx-1032]{1to2}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5{k7}, QWORD PTR [edx+1016]{1to2}, 123 # AVX512{DQ,VL} Disp8
+ vfpclasspd k5{k7}, QWORD PTR [edx+1024]{1to2}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5{k7}, QWORD PTR [edx-1024]{1to2}, 123 # AVX512{DQ,VL} Disp8
+ vfpclasspd k5{k7}, QWORD PTR [edx-1032]{1to2}, 123 # AVX512{DQ,VL}
vfpclasspd k5{k7}, ymm6, 0xab # AVX512{DQ,VL}
vfpclasspd k5{k7}, ymm6, 123 # AVX512{DQ,VL}
vfpclasspd k5{k7}, YMMWORD PTR [ecx], 123 # AVX512{DQ,VL}
vfpclasspd k5{k7}, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512{DQ,VL}
- vfpclasspdy k5{k7}, [eax]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5{k7}, [eax]{1to4}, 123 # AVX512{DQ,VL}
vfpclasspd k5{k7}, YMMWORD PTR [edx+4064], 123 # AVX512{DQ,VL} Disp8
vfpclasspd k5{k7}, YMMWORD PTR [edx+4096], 123 # AVX512{DQ,VL}
vfpclasspd k5{k7}, YMMWORD PTR [edx-4096], 123 # AVX512{DQ,VL} Disp8
vfpclasspd k5{k7}, YMMWORD PTR [edx-4128], 123 # AVX512{DQ,VL}
- vfpclasspdy k5{k7}, [edx+1016]{1to4}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspdy k5{k7}, [edx+1024]{1to4}, 123 # AVX512{DQ,VL}
- vfpclasspdy k5{k7}, [edx-1024]{1to4}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspdy k5{k7}, [edx-1032]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5{k7}, QWORD PTR [edx+1016]{1to4}, 123 # AVX512{DQ,VL} Disp8
+ vfpclasspd k5{k7}, QWORD PTR [edx+1024]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5{k7}, QWORD PTR [edx-1024]{1to4}, 123 # AVX512{DQ,VL} Disp8
+ vfpclasspd k5{k7}, QWORD PTR [edx-1032]{1to4}, 123 # AVX512{DQ,VL}
vfpclassps k5{k7}, xmm6, 0xab # AVX512{DQ,VL}
vfpclassps k5{k7}, xmm6, 123 # AVX512{DQ,VL}
vfpclassps k5{k7}, XMMWORD PTR [ecx], 123 # AVX512{DQ,VL}
vfpclassps k5{k7}, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512{DQ,VL}
- vfpclasspsx k5{k7}, [eax]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclassps k5{k7}, [eax]{1to4}, 123 # AVX512{DQ,VL}
vfpclassps k5{k7}, XMMWORD PTR [edx+2032], 123 # AVX512{DQ,VL} Disp8
vfpclassps k5{k7}, XMMWORD PTR [edx+2048], 123 # AVX512{DQ,VL}
vfpclassps k5{k7}, XMMWORD PTR [edx-2048], 123 # AVX512{DQ,VL} Disp8
vfpclassps k5{k7}, XMMWORD PTR [edx-2064], 123 # AVX512{DQ,VL}
- vfpclasspsx k5{k7}, [edx+508]{1to4}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspsx k5{k7}, [edx+512]{1to4}, 123 # AVX512{DQ,VL}
- vfpclasspsx k5{k7}, [edx-512]{1to4}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspsx k5{k7}, [edx-516]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclassps k5{k7}, DWORD PTR [edx+508]{1to4}, 123 # AVX512{DQ,VL} Disp8
+ vfpclassps k5{k7}, DWORD PTR [edx+512]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclassps k5{k7}, DWORD PTR [edx-512]{1to4}, 123 # AVX512{DQ,VL} Disp8
+ vfpclassps k5{k7}, DWORD PTR [edx-516]{1to4}, 123 # AVX512{DQ,VL}
vfpclassps k5{k7}, ymm6, 0xab # AVX512{DQ,VL}
vfpclassps k5{k7}, ymm6, 123 # AVX512{DQ,VL}
vfpclassps k5{k7}, YMMWORD PTR [ecx], 123 # AVX512{DQ,VL}
vfpclassps k5{k7}, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512{DQ,VL}
- vfpclasspsy k5{k7}, [eax]{1to8}, 123 # AVX512{DQ,VL}
+ vfpclassps k5{k7}, [eax]{1to8}, 123 # AVX512{DQ,VL}
vfpclassps k5{k7}, YMMWORD PTR [edx+4064], 123 # AVX512{DQ,VL} Disp8
vfpclassps k5{k7}, YMMWORD PTR [edx+4096], 123 # AVX512{DQ,VL}
vfpclassps k5{k7}, YMMWORD PTR [edx-4096], 123 # AVX512{DQ,VL} Disp8
vfpclassps k5{k7}, YMMWORD PTR [edx-4128], 123 # AVX512{DQ,VL}
- vfpclasspsy k5{k7}, [edx+508]{1to8}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspsy k5{k7}, [edx+512]{1to8}, 123 # AVX512{DQ,VL}
- vfpclasspsy k5{k7}, [edx-512]{1to8}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspsy k5{k7}, [edx-516]{1to8}, 123 # AVX512{DQ,VL}
+ vfpclassps k5{k7}, DWORD PTR [edx+508]{1to8}, 123 # AVX512{DQ,VL} Disp8
+ vfpclassps k5{k7}, DWORD PTR [edx+512]{1to8}, 123 # AVX512{DQ,VL}
+ vfpclassps k5{k7}, DWORD PTR [edx-512]{1to8}, 123 # AVX512{DQ,VL} Disp8
+ vfpclassps k5{k7}, DWORD PTR [edx-516]{1to8}, 123 # AVX512{DQ,VL}
vinsertf64x2 ymm6{k7}, ymm5, xmm4, 0xab # AVX512{DQ,VL}
vinsertf64x2 ymm6{k7}{z}, ymm5, xmm4, 0xab # AVX512{DQ,VL}
vinsertf64x2 ymm6{k7}, ymm5, xmm4, 123 # AVX512{DQ,VL}
--- 2015-04-16/gas/testsuite/gas/i386/avx512f_vl.s
+++ 2015-04-16/gas/testsuite/gas/i386/avx512f_vl.s
@@ -316,7 +316,7 @@ _start:
vcvtpd2dq %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vcvtpd2dqx (%ecx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2dqx -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
- vcvtpd2dqx (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
+ vcvtpd2dq (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
vcvtpd2dqx 2032(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vcvtpd2dqx 2048(%edx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2dqx -2048(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
@@ -329,7 +329,7 @@ _start:
vcvtpd2dq %ymm5, %xmm6{%k7}{z} # AVX512{F,VL}
vcvtpd2dqy (%ecx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2dqy -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
- vcvtpd2dqy (%eax){1to4}, %xmm6{%k7} # AVX512{F,VL}
+ vcvtpd2dq (%eax){1to4}, %xmm6{%k7} # AVX512{F,VL}
vcvtpd2dqy 4064(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vcvtpd2dqy 4096(%edx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2dqy -4096(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
@@ -342,7 +342,7 @@ _start:
vcvtpd2ps %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vcvtpd2psx (%ecx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2psx -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
- vcvtpd2psx (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
+ vcvtpd2ps (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
vcvtpd2psx 2032(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vcvtpd2psx 2048(%edx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2psx -2048(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
@@ -355,7 +355,7 @@ _start:
vcvtpd2ps %ymm5, %xmm6{%k7}{z} # AVX512{F,VL}
vcvtpd2psy (%ecx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2psy -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
- vcvtpd2psy (%eax){1to4}, %xmm6{%k7} # AVX512{F,VL}
+ vcvtpd2ps (%eax){1to4}, %xmm6{%k7} # AVX512{F,VL}
vcvtpd2psy 4064(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vcvtpd2psy 4096(%edx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2psy -4096(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
@@ -368,7 +368,7 @@ _start:
vcvtpd2udq %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vcvtpd2udqx (%ecx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2udqx -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
- vcvtpd2udqx (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
+ vcvtpd2udq (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
vcvtpd2udqx 2032(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vcvtpd2udqx 2048(%edx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2udqx -2048(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
@@ -381,7 +381,7 @@ _start:
vcvtpd2udq %ymm5, %xmm6{%k7}{z} # AVX512{F,VL}
vcvtpd2udqy (%ecx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2udqy -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
- vcvtpd2udqy (%eax){1to4}, %xmm6{%k7} # AVX512{F,VL}
+ vcvtpd2udq (%eax){1to4}, %xmm6{%k7} # AVX512{F,VL}
vcvtpd2udqy 4064(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vcvtpd2udqy 4096(%edx), %xmm6{%k7} # AVX512{F,VL}
vcvtpd2udqy -4096(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
@@ -494,7 +494,7 @@ _start:
vcvttpd2dq %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vcvttpd2dqx (%ecx), %xmm6{%k7} # AVX512{F,VL}
vcvttpd2dqx -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
- vcvttpd2dqx (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
+ vcvttpd2dq (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
vcvttpd2dqx 2032(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vcvttpd2dqx 2048(%edx), %xmm6{%k7} # AVX512{F,VL}
vcvttpd2dqx -2048(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
@@ -507,7 +507,7 @@ _start:
vcvttpd2dq %ymm5, %xmm6{%k7}{z} # AVX512{F,VL}
vcvttpd2dqy (%ecx), %xmm6{%k7} # AVX512{F,VL}
vcvttpd2dqy -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
- vcvttpd2dqy (%eax){1to4}, %xmm6{%k7} # AVX512{F,VL}
+ vcvttpd2dq (%eax){1to4}, %xmm6{%k7} # AVX512{F,VL}
vcvttpd2dqy 4064(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vcvttpd2dqy 4096(%edx), %xmm6{%k7} # AVX512{F,VL}
vcvttpd2dqy -4096(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
@@ -5498,7 +5498,7 @@ _start:
vcvttpd2udq %xmm5, %xmm6{%k7}{z} # AVX512{F,VL}
vcvttpd2udqx (%ecx), %xmm6{%k7} # AVX512{F,VL}
vcvttpd2udqx -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
- vcvttpd2udqx (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
+ vcvttpd2udq (%eax){1to2}, %xmm6{%k7} # AVX512{F,VL}
vcvttpd2udqx 2032(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vcvttpd2udqx 2048(%edx), %xmm6{%k7} # AVX512{F,VL}
vcvttpd2udqx -2048(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
@@ -5511,7 +5511,7 @@ _start:
vcvttpd2udq %ymm5, %xmm6{%k7}{z} # AVX512{F,VL}
vcvttpd2udqy (%ecx), %xmm6{%k7} # AVX512{F,VL}
vcvttpd2udqy -123456(%esp,%esi,8), %xmm6{%k7} # AVX512{F,VL}
- vcvttpd2udqy (%eax){1to4}, %xmm6{%k7} # AVX512{F,VL}
+ vcvttpd2udq (%eax){1to4}, %xmm6{%k7} # AVX512{F,VL}
vcvttpd2udqy 4064(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
vcvttpd2udqy 4096(%edx), %xmm6{%k7} # AVX512{F,VL}
vcvttpd2udqy -4096(%edx), %xmm6{%k7} # AVX512{F,VL} Disp8
@@ -6013,80 +6013,80 @@ _start:
vcvtpd2dq xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vcvtpd2dq xmm6{k7}, XMMWORD PTR [ecx] # AVX512{F,VL}
vcvtpd2dq xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
- vcvtpd2dqx xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
+ vcvtpd2dq xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
vcvtpd2dq xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{F,VL} Disp8
vcvtpd2dq xmm6{k7}, XMMWORD PTR [edx+2048] # AVX512{F,VL}
vcvtpd2dq xmm6{k7}, XMMWORD PTR [edx-2048] # AVX512{F,VL} Disp8
vcvtpd2dq xmm6{k7}, XMMWORD PTR [edx-2064] # AVX512{F,VL}
- vcvtpd2dqx xmm6{k7}, [edx+1016]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2dqx xmm6{k7}, [edx+1024]{1to2} # AVX512{F,VL}
- vcvtpd2dqx xmm6{k7}, [edx-1024]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2dqx xmm6{k7}, [edx-1032]{1to2} # AVX512{F,VL}
+ vcvtpd2dq xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2dq xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{F,VL}
+ vcvtpd2dq xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2dq xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{F,VL}
vcvtpd2dq xmm6{k7}, ymm5 # AVX512{F,VL}
vcvtpd2dq xmm6{k7}{z}, ymm5 # AVX512{F,VL}
vcvtpd2dq xmm6{k7}, YMMWORD PTR [ecx] # AVX512{F,VL}
vcvtpd2dq xmm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
- vcvtpd2dqy xmm6{k7}, [eax]{1to4} # AVX512{F,VL}
+ vcvtpd2dq xmm6{k7}, [eax]{1to4} # AVX512{F,VL}
vcvtpd2dq xmm6{k7}, YMMWORD PTR [edx+4064] # AVX512{F,VL} Disp8
vcvtpd2dq xmm6{k7}, YMMWORD PTR [edx+4096] # AVX512{F,VL}
vcvtpd2dq xmm6{k7}, YMMWORD PTR [edx-4096] # AVX512{F,VL} Disp8
vcvtpd2dq xmm6{k7}, YMMWORD PTR [edx-4128] # AVX512{F,VL}
- vcvtpd2dqy xmm6{k7}, [edx+1016]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2dqy xmm6{k7}, [edx+1024]{1to4} # AVX512{F,VL}
- vcvtpd2dqy xmm6{k7}, [edx-1024]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2dqy xmm6{k7}, [edx-1032]{1to4} # AVX512{F,VL}
+ vcvtpd2dq xmm6{k7}, QWORD PTR [edx+1016]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2dq xmm6{k7}, QWORD PTR [edx+1024]{1to4} # AVX512{F,VL}
+ vcvtpd2dq xmm6{k7}, QWORD PTR [edx-1024]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2dq xmm6{k7}, QWORD PTR [edx-1032]{1to4} # AVX512{F,VL}
vcvtpd2ps xmm6{k7}, xmm5 # AVX512{F,VL}
vcvtpd2ps xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vcvtpd2ps xmm6{k7}, XMMWORD PTR [ecx] # AVX512{F,VL}
vcvtpd2ps xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
- vcvtpd2psx xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
+ vcvtpd2ps xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
vcvtpd2ps xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{F,VL} Disp8
vcvtpd2ps xmm6{k7}, XMMWORD PTR [edx+2048] # AVX512{F,VL}
vcvtpd2ps xmm6{k7}, XMMWORD PTR [edx-2048] # AVX512{F,VL} Disp8
vcvtpd2ps xmm6{k7}, XMMWORD PTR [edx-2064] # AVX512{F,VL}
- vcvtpd2psx xmm6{k7}, [edx+1016]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2psx xmm6{k7}, [edx+1024]{1to2} # AVX512{F,VL}
- vcvtpd2psx xmm6{k7}, [edx-1024]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2psx xmm6{k7}, [edx-1032]{1to2} # AVX512{F,VL}
+ vcvtpd2ps xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2ps xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{F,VL}
+ vcvtpd2ps xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2ps xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{F,VL}
vcvtpd2ps xmm6{k7}, ymm5 # AVX512{F,VL}
vcvtpd2ps xmm6{k7}{z}, ymm5 # AVX512{F,VL}
vcvtpd2ps xmm6{k7}, YMMWORD PTR [ecx] # AVX512{F,VL}
vcvtpd2ps xmm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
- vcvtpd2psy xmm6{k7}, [eax]{1to4} # AVX512{F,VL}
+ vcvtpd2ps xmm6{k7}, [eax]{1to4} # AVX512{F,VL}
vcvtpd2ps xmm6{k7}, YMMWORD PTR [edx+4064] # AVX512{F,VL} Disp8
vcvtpd2ps xmm6{k7}, YMMWORD PTR [edx+4096] # AVX512{F,VL}
vcvtpd2ps xmm6{k7}, YMMWORD PTR [edx-4096] # AVX512{F,VL} Disp8
vcvtpd2ps xmm6{k7}, YMMWORD PTR [edx-4128] # AVX512{F,VL}
- vcvtpd2psy xmm6{k7}, [edx+1016]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2psy xmm6{k7}, [edx+1024]{1to4} # AVX512{F,VL}
- vcvtpd2psy xmm6{k7}, [edx-1024]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2psy xmm6{k7}, [edx-1032]{1to4} # AVX512{F,VL}
+ vcvtpd2ps xmm6{k7}, QWORD PTR [edx+1016]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2ps xmm6{k7}, QWORD PTR [edx+1024]{1to4} # AVX512{F,VL}
+ vcvtpd2ps xmm6{k7}, QWORD PTR [edx-1024]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2ps xmm6{k7}, QWORD PTR [edx-1032]{1to4} # AVX512{F,VL}
vcvtpd2udq xmm6{k7}, xmm5 # AVX512{F,VL}
vcvtpd2udq xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vcvtpd2udq xmm6{k7}, XMMWORD PTR [ecx] # AVX512{F,VL}
vcvtpd2udq xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
- vcvtpd2udqx xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
+ vcvtpd2udq xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
vcvtpd2udq xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{F,VL} Disp8
vcvtpd2udq xmm6{k7}, XMMWORD PTR [edx+2048] # AVX512{F,VL}
vcvtpd2udq xmm6{k7}, XMMWORD PTR [edx-2048] # AVX512{F,VL} Disp8
vcvtpd2udq xmm6{k7}, XMMWORD PTR [edx-2064] # AVX512{F,VL}
- vcvtpd2udqx xmm6{k7}, [edx+1016]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2udqx xmm6{k7}, [edx+1024]{1to2} # AVX512{F,VL}
- vcvtpd2udqx xmm6{k7}, [edx-1024]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2udqx xmm6{k7}, [edx-1032]{1to2} # AVX512{F,VL}
+ vcvtpd2udq xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2udq xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{F,VL}
+ vcvtpd2udq xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2udq xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{F,VL}
vcvtpd2udq xmm6{k7}, ymm5 # AVX512{F,VL}
vcvtpd2udq xmm6{k7}{z}, ymm5 # AVX512{F,VL}
vcvtpd2udq xmm6{k7}, YMMWORD PTR [ecx] # AVX512{F,VL}
vcvtpd2udq xmm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
- vcvtpd2udqy xmm6{k7}, [eax]{1to4} # AVX512{F,VL}
+ vcvtpd2udq xmm6{k7}, [eax]{1to4} # AVX512{F,VL}
vcvtpd2udq xmm6{k7}, YMMWORD PTR [edx+4064] # AVX512{F,VL} Disp8
vcvtpd2udq xmm6{k7}, YMMWORD PTR [edx+4096] # AVX512{F,VL}
vcvtpd2udq xmm6{k7}, YMMWORD PTR [edx-4096] # AVX512{F,VL} Disp8
vcvtpd2udq xmm6{k7}, YMMWORD PTR [edx-4128] # AVX512{F,VL}
- vcvtpd2udqy xmm6{k7}, [edx+1016]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2udqy xmm6{k7}, [edx+1024]{1to4} # AVX512{F,VL}
- vcvtpd2udqy xmm6{k7}, [edx-1024]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2udqy xmm6{k7}, [edx-1032]{1to4} # AVX512{F,VL}
+ vcvtpd2udq xmm6{k7}, QWORD PTR [edx+1016]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2udq xmm6{k7}, QWORD PTR [edx+1024]{1to4} # AVX512{F,VL}
+ vcvtpd2udq xmm6{k7}, QWORD PTR [edx-1024]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2udq xmm6{k7}, QWORD PTR [edx-1032]{1to4} # AVX512{F,VL}
vcvtph2ps xmm6{k7}, xmm5 # AVX512{F,VL}
vcvtph2ps xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vcvtph2ps xmm6{k7}, QWORD PTR [ecx] # AVX512{F,VL}
@@ -6191,28 +6191,28 @@ _start:
vcvttpd2dq xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vcvttpd2dq xmm6{k7}, XMMWORD PTR [ecx] # AVX512{F,VL}
vcvttpd2dq xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
- vcvttpd2dqx xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
+ vcvttpd2dq xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
vcvttpd2dq xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{F,VL} Disp8
vcvttpd2dq xmm6{k7}, XMMWORD PTR [edx+2048] # AVX512{F,VL}
vcvttpd2dq xmm6{k7}, XMMWORD PTR [edx-2048] # AVX512{F,VL} Disp8
vcvttpd2dq xmm6{k7}, XMMWORD PTR [edx-2064] # AVX512{F,VL}
- vcvttpd2dqx xmm6{k7}, [edx+1016]{1to2} # AVX512{F,VL} Disp8
- vcvttpd2dqx xmm6{k7}, [edx+1024]{1to2} # AVX512{F,VL}
- vcvttpd2dqx xmm6{k7}, [edx-1024]{1to2} # AVX512{F,VL} Disp8
- vcvttpd2dqx xmm6{k7}, [edx-1032]{1to2} # AVX512{F,VL}
+ vcvttpd2dq xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{F,VL} Disp8
+ vcvttpd2dq xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{F,VL}
+ vcvttpd2dq xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{F,VL} Disp8
+ vcvttpd2dq xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{F,VL}
vcvttpd2dq xmm6{k7}, ymm5 # AVX512{F,VL}
vcvttpd2dq xmm6{k7}{z}, ymm5 # AVX512{F,VL}
vcvttpd2dq xmm6{k7}, YMMWORD PTR [ecx] # AVX512{F,VL}
vcvttpd2dq xmm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
- vcvttpd2dqy xmm6{k7}, [eax]{1to4} # AVX512{F,VL}
+ vcvttpd2dq xmm6{k7}, [eax]{1to4} # AVX512{F,VL}
vcvttpd2dq xmm6{k7}, YMMWORD PTR [edx+4064] # AVX512{F,VL} Disp8
vcvttpd2dq xmm6{k7}, YMMWORD PTR [edx+4096] # AVX512{F,VL}
vcvttpd2dq xmm6{k7}, YMMWORD PTR [edx-4096] # AVX512{F,VL} Disp8
vcvttpd2dq xmm6{k7}, YMMWORD PTR [edx-4128] # AVX512{F,VL}
- vcvttpd2dqy xmm6{k7}, [edx+1016]{1to4} # AVX512{F,VL} Disp8
- vcvttpd2dqy xmm6{k7}, [edx+1024]{1to4} # AVX512{F,VL}
- vcvttpd2dqy xmm6{k7}, [edx-1024]{1to4} # AVX512{F,VL} Disp8
- vcvttpd2dqy xmm6{k7}, [edx-1032]{1to4} # AVX512{F,VL}
+ vcvttpd2dq xmm6{k7}, QWORD PTR [edx+1016]{1to4} # AVX512{F,VL} Disp8
+ vcvttpd2dq xmm6{k7}, QWORD PTR [edx+1024]{1to4} # AVX512{F,VL}
+ vcvttpd2dq xmm6{k7}, QWORD PTR [edx-1024]{1to4} # AVX512{F,VL} Disp8
+ vcvttpd2dq xmm6{k7}, QWORD PTR [edx-1032]{1to4} # AVX512{F,VL}
vcvttps2dq xmm6{k7}, xmm5 # AVX512{F,VL}
vcvttps2dq xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vcvttps2dq xmm6{k7}, XMMWORD PTR [ecx] # AVX512{F,VL}
@@ -11195,28 +11195,28 @@ _start:
vcvttpd2udq xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vcvttpd2udq xmm6{k7}, XMMWORD PTR [ecx] # AVX512{F,VL}
vcvttpd2udq xmm6{k7}, XMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
- vcvttpd2udqx xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
+ vcvttpd2udq xmm6{k7}, [eax]{1to2} # AVX512{F,VL}
vcvttpd2udq xmm6{k7}, XMMWORD PTR [edx+2032] # AVX512{F,VL} Disp8
vcvttpd2udq xmm6{k7}, XMMWORD PTR [edx+2048] # AVX512{F,VL}
vcvttpd2udq xmm6{k7}, XMMWORD PTR [edx-2048] # AVX512{F,VL} Disp8
vcvttpd2udq xmm6{k7}, XMMWORD PTR [edx-2064] # AVX512{F,VL}
- vcvttpd2udqx xmm6{k7}, [edx+1016]{1to2} # AVX512{F,VL} Disp8
- vcvttpd2udqx xmm6{k7}, [edx+1024]{1to2} # AVX512{F,VL}
- vcvttpd2udqx xmm6{k7}, [edx-1024]{1to2} # AVX512{F,VL} Disp8
- vcvttpd2udqx xmm6{k7}, [edx-1032]{1to2} # AVX512{F,VL}
+ vcvttpd2udq xmm6{k7}, QWORD PTR [edx+1016]{1to2} # AVX512{F,VL} Disp8
+ vcvttpd2udq xmm6{k7}, QWORD PTR [edx+1024]{1to2} # AVX512{F,VL}
+ vcvttpd2udq xmm6{k7}, QWORD PTR [edx-1024]{1to2} # AVX512{F,VL} Disp8
+ vcvttpd2udq xmm6{k7}, QWORD PTR [edx-1032]{1to2} # AVX512{F,VL}
vcvttpd2udq xmm6{k7}, ymm5 # AVX512{F,VL}
vcvttpd2udq xmm6{k7}{z}, ymm5 # AVX512{F,VL}
vcvttpd2udq xmm6{k7}, YMMWORD PTR [ecx] # AVX512{F,VL}
vcvttpd2udq xmm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512{F,VL}
- vcvttpd2udqy xmm6{k7}, [eax]{1to4} # AVX512{F,VL}
+ vcvttpd2udq xmm6{k7}, [eax]{1to4} # AVX512{F,VL}
vcvttpd2udq xmm6{k7}, YMMWORD PTR [edx+4064] # AVX512{F,VL} Disp8
vcvttpd2udq xmm6{k7}, YMMWORD PTR [edx+4096] # AVX512{F,VL}
vcvttpd2udq xmm6{k7}, YMMWORD PTR [edx-4096] # AVX512{F,VL} Disp8
vcvttpd2udq xmm6{k7}, YMMWORD PTR [edx-4128] # AVX512{F,VL}
- vcvttpd2udqy xmm6{k7}, [edx+1016]{1to4} # AVX512{F,VL} Disp8
- vcvttpd2udqy xmm6{k7}, [edx+1024]{1to4} # AVX512{F,VL}
- vcvttpd2udqy xmm6{k7}, [edx-1024]{1to4} # AVX512{F,VL} Disp8
- vcvttpd2udqy xmm6{k7}, [edx-1032]{1to4} # AVX512{F,VL}
+ vcvttpd2udq xmm6{k7}, QWORD PTR [edx+1016]{1to4} # AVX512{F,VL} Disp8
+ vcvttpd2udq xmm6{k7}, QWORD PTR [edx+1024]{1to4} # AVX512{F,VL}
+ vcvttpd2udq xmm6{k7}, QWORD PTR [edx-1024]{1to4} # AVX512{F,VL} Disp8
+ vcvttpd2udq xmm6{k7}, QWORD PTR [edx-1032]{1to4} # AVX512{F,VL}
vcvttps2udq xmm6{k7}, xmm5 # AVX512{F,VL}
vcvttps2udq xmm6{k7}{z}, xmm5 # AVX512{F,VL}
vcvttps2udq xmm6{k7}, XMMWORD PTR [ecx] # AVX512{F,VL}
--- 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512dq.s
+++ 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512dq.s
@@ -209,7 +209,7 @@ _start:
vfpclasspd $123, %zmm30, %k5 # AVX512DQ
vfpclasspdz $123, (%rcx), %k5 # AVX512DQ
vfpclasspdz $123, 0x123(%rax,%r14,8), %k5 # AVX512DQ
- vfpclasspdz $123, (%rcx){1to8}, %k5 # AVX512DQ
+ vfpclasspd $123, (%rcx){1to8}, %k5 # AVX512DQ
vfpclasspdz $123, 8128(%rdx), %k5 # AVX512DQ Disp8
vfpclasspdz $123, 8192(%rdx), %k5 # AVX512DQ
vfpclasspdz $123, -8192(%rdx), %k5 # AVX512DQ Disp8
@@ -223,7 +223,7 @@ _start:
vfpclassps $123, %zmm30, %k5 # AVX512DQ
vfpclasspsz $123, (%rcx), %k5 # AVX512DQ
vfpclasspsz $123, 0x123(%rax,%r14,8), %k5 # AVX512DQ
- vfpclasspsz $123, (%rcx){1to16}, %k5 # AVX512DQ
+ vfpclassps $123, (%rcx){1to16}, %k5 # AVX512DQ
vfpclasspsz $123, 8128(%rdx), %k5 # AVX512DQ Disp8
vfpclasspsz $123, 8192(%rdx), %k5 # AVX512DQ
vfpclasspsz $123, -8192(%rdx), %k5 # AVX512DQ Disp8
@@ -909,29 +909,29 @@ _start:
vfpclasspd k5, zmm30, 123 # AVX512DQ
vfpclasspd k5, ZMMWORD PTR [rcx], 123 # AVX512DQ
vfpclasspd k5, ZMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512DQ
- vfpclasspdz k5, [rcx]{1to8}, 123 # AVX512DQ
+ vfpclasspd k5, [rcx]{1to8}, 123 # AVX512DQ
vfpclasspd k5, ZMMWORD PTR [rdx+8128], 123 # AVX512DQ Disp8
vfpclasspd k5, ZMMWORD PTR [rdx+8192], 123 # AVX512DQ
vfpclasspd k5, ZMMWORD PTR [rdx-8192], 123 # AVX512DQ Disp8
vfpclasspd k5, ZMMWORD PTR [rdx-8256], 123 # AVX512DQ
- vfpclasspdz k5, [rdx+1016]{1to8}, 123 # AVX512DQ Disp8
- vfpclasspdz k5, [rdx+1024]{1to8}, 123 # AVX512DQ
- vfpclasspdz k5, [rdx-1024]{1to8}, 123 # AVX512DQ Disp8
- vfpclasspdz k5, [rdx-1032]{1to8}, 123 # AVX512DQ
+ vfpclasspd k5, QWORD PTR [rdx+1016]{1to8}, 123 # AVX512DQ Disp8
+ vfpclasspd k5, QWORD PTR [rdx+1024]{1to8}, 123 # AVX512DQ
+ vfpclasspd k5, QWORD PTR [rdx-1024]{1to8}, 123 # AVX512DQ Disp8
+ vfpclasspd k5, QWORD PTR [rdx-1032]{1to8}, 123 # AVX512DQ
vfpclassps k5, zmm30, 0xab # AVX512DQ
vfpclassps k5{k7}, zmm30, 0xab # AVX512DQ
vfpclassps k5, zmm30, 123 # AVX512DQ
vfpclassps k5, ZMMWORD PTR [rcx], 123 # AVX512DQ
vfpclassps k5, ZMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512DQ
- vfpclasspsz k5, [rcx]{1to16}, 123 # AVX512DQ
+ vfpclassps k5, [rcx]{1to16}, 123 # AVX512DQ
vfpclassps k5, ZMMWORD PTR [rdx+8128], 123 # AVX512DQ Disp8
vfpclassps k5, ZMMWORD PTR [rdx+8192], 123 # AVX512DQ
vfpclassps k5, ZMMWORD PTR [rdx-8192], 123 # AVX512DQ Disp8
vfpclassps k5, ZMMWORD PTR [rdx-8256], 123 # AVX512DQ
- vfpclasspsz k5, [rdx+508]{1to16}, 123 # AVX512DQ Disp8
- vfpclasspsz k5, [rdx+512]{1to16}, 123 # AVX512DQ
- vfpclasspsz k5, [rdx-512]{1to16}, 123 # AVX512DQ Disp8
- vfpclasspsz k5, [rdx-516]{1to16}, 123 # AVX512DQ
+ vfpclassps k5, DWORD PTR [rdx+508]{1to16}, 123 # AVX512DQ Disp8
+ vfpclassps k5, DWORD PTR [rdx+512]{1to16}, 123 # AVX512DQ
+ vfpclassps k5, DWORD PTR [rdx-512]{1to16}, 123 # AVX512DQ Disp8
+ vfpclassps k5, DWORD PTR [rdx-516]{1to16}, 123 # AVX512DQ
vfpclasssd k5, xmm30, 0xab # AVX512DQ
vfpclasssd k5{k7}, xmm30, 0xab # AVX512DQ
vfpclasssd k5, xmm30, 123 # AVX512DQ
--- 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512dq_vl.s
+++ 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512dq_vl.s
@@ -173,7 +173,7 @@ _start:
vcvtqq2ps %xmm29, %xmm30{%k7}{z} # AVX512{DQ,VL}
vcvtqq2psx (%rcx), %xmm30 # AVX512{DQ,VL}
vcvtqq2psx 0x123(%rax,%r14,8), %xmm30 # AVX512{DQ,VL}
- vcvtqq2psx (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
+ vcvtqq2ps (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
vcvtqq2psx 2032(%rdx), %xmm30 # AVX512{DQ,VL} Disp8
vcvtqq2psx 2048(%rdx), %xmm30 # AVX512{DQ,VL}
vcvtqq2psx -2048(%rdx), %xmm30 # AVX512{DQ,VL} Disp8
@@ -187,7 +187,7 @@ _start:
vcvtqq2ps %ymm29, %xmm30{%k7}{z} # AVX512{DQ,VL}
vcvtqq2psy (%rcx), %xmm30 # AVX512{DQ,VL}
vcvtqq2psy 0x123(%rax,%r14,8), %xmm30 # AVX512{DQ,VL}
- vcvtqq2psy (%rcx){1to4}, %xmm30 # AVX512{DQ,VL}
+ vcvtqq2ps (%rcx){1to4}, %xmm30 # AVX512{DQ,VL}
vcvtqq2psy 4064(%rdx), %xmm30 # AVX512{DQ,VL} Disp8
vcvtqq2psy 4096(%rdx), %xmm30 # AVX512{DQ,VL}
vcvtqq2psy -4096(%rdx), %xmm30 # AVX512{DQ,VL} Disp8
@@ -229,7 +229,7 @@ _start:
vcvtuqq2ps %xmm29, %xmm30{%k7}{z} # AVX512{DQ,VL}
vcvtuqq2psx (%rcx), %xmm30 # AVX512{DQ,VL}
vcvtuqq2psx 0x123(%rax,%r14,8), %xmm30 # AVX512{DQ,VL}
- vcvtuqq2psx (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
+ vcvtuqq2ps (%rcx){1to2}, %xmm30 # AVX512{DQ,VL}
vcvtuqq2psx 2032(%rdx), %xmm30 # AVX512{DQ,VL} Disp8
vcvtuqq2psx 2048(%rdx), %xmm30 # AVX512{DQ,VL}
vcvtuqq2psx -2048(%rdx), %xmm30 # AVX512{DQ,VL} Disp8
@@ -243,7 +243,7 @@ _start:
vcvtuqq2ps %ymm29, %xmm30{%k7}{z} # AVX512{DQ,VL}
vcvtuqq2psy (%rcx), %xmm30 # AVX512{DQ,VL}
vcvtuqq2psy 0x123(%rax,%r14,8), %xmm30 # AVX512{DQ,VL}
- vcvtuqq2psy (%rcx){1to4}, %xmm30 # AVX512{DQ,VL}
+ vcvtuqq2ps (%rcx){1to4}, %xmm30 # AVX512{DQ,VL}
vcvtuqq2psy 4064(%rdx), %xmm30 # AVX512{DQ,VL} Disp8
vcvtuqq2psy 4096(%rdx), %xmm30 # AVX512{DQ,VL}
vcvtuqq2psy -4096(%rdx), %xmm30 # AVX512{DQ,VL} Disp8
@@ -265,7 +265,7 @@ _start:
vfpclasspd $123, %xmm30, %k5 # AVX512{DQ,VL}
vfpclasspdx $123, (%rcx), %k5 # AVX512{DQ,VL}
vfpclasspdx $123, 0x123(%rax,%r14,8), %k5 # AVX512{DQ,VL}
- vfpclasspdx $123, (%rcx){1to2}, %k5 # AVX512{DQ,VL}
+ vfpclasspd $123, (%rcx){1to2}, %k5 # AVX512{DQ,VL}
vfpclasspdx $123, 2032(%rdx), %k5 # AVX512{DQ,VL} Disp8
vfpclasspdx $123, 2048(%rdx), %k5 # AVX512{DQ,VL}
vfpclasspdx $123, -2048(%rdx), %k5 # AVX512{DQ,VL} Disp8
@@ -279,7 +279,7 @@ _start:
vfpclasspd $123, %ymm30, %k5 # AVX512{DQ,VL}
vfpclasspdy $123, (%rcx), %k5 # AVX512{DQ,VL}
vfpclasspdy $123, 0x123(%rax,%r14,8), %k5 # AVX512{DQ,VL}
- vfpclasspdy $123, (%rcx){1to4}, %k5 # AVX512{DQ,VL}
+ vfpclasspd $123, (%rcx){1to4}, %k5 # AVX512{DQ,VL}
vfpclasspdy $123, 4064(%rdx), %k5 # AVX512{DQ,VL} Disp8
vfpclasspdy $123, 4096(%rdx), %k5 # AVX512{DQ,VL}
vfpclasspdy $123, -4096(%rdx), %k5 # AVX512{DQ,VL} Disp8
@@ -293,7 +293,7 @@ _start:
vfpclassps $123, %xmm30, %k5 # AVX512{DQ,VL}
vfpclasspsx $123, (%rcx), %k5 # AVX512{DQ,VL}
vfpclasspsx $123, 0x123(%rax,%r14,8), %k5 # AVX512{DQ,VL}
- vfpclasspsx $123, (%rcx){1to4}, %k5 # AVX512{DQ,VL}
+ vfpclassps $123, (%rcx){1to4}, %k5 # AVX512{DQ,VL}
vfpclasspsx $123, 2032(%rdx), %k5 # AVX512{DQ,VL} Disp8
vfpclasspsx $123, 2048(%rdx), %k5 # AVX512{DQ,VL}
vfpclasspsx $123, -2048(%rdx), %k5 # AVX512{DQ,VL} Disp8
@@ -307,7 +307,7 @@ _start:
vfpclassps $123, %ymm30, %k5 # AVX512{DQ,VL}
vfpclasspsy $123, (%rcx), %k5 # AVX512{DQ,VL}
vfpclasspsy $123, 0x123(%rax,%r14,8), %k5 # AVX512{DQ,VL}
- vfpclasspsy $123, (%rcx){1to8}, %k5 # AVX512{DQ,VL}
+ vfpclassps $123, (%rcx){1to8}, %k5 # AVX512{DQ,VL}
vfpclasspsy $123, 4064(%rdx), %k5 # AVX512{DQ,VL} Disp8
vfpclasspsy $123, 4096(%rdx), %k5 # AVX512{DQ,VL}
vfpclasspsy $123, -4096(%rdx), %k5 # AVX512{DQ,VL} Disp8
@@ -1034,29 +1034,29 @@ _start:
vcvtqq2ps xmm30{k7}{z}, xmm29 # AVX512{DQ,VL}
vcvtqq2ps xmm30, XMMWORD PTR [rcx] # AVX512{DQ,VL}
vcvtqq2ps xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{DQ,VL}
- vcvtqq2psx xmm30, [rcx]{1to2} # AVX512{DQ,VL}
+ vcvtqq2ps xmm30, [rcx]{1to2} # AVX512{DQ,VL}
vcvtqq2ps xmm30, XMMWORD PTR [rdx+2032] # AVX512{DQ,VL} Disp8
vcvtqq2ps xmm30, XMMWORD PTR [rdx+2048] # AVX512{DQ,VL}
vcvtqq2ps xmm30, XMMWORD PTR [rdx-2048] # AVX512{DQ,VL} Disp8
vcvtqq2ps xmm30, XMMWORD PTR [rdx-2064] # AVX512{DQ,VL}
- vcvtqq2psx xmm30, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
- vcvtqq2psx xmm30, [rdx+1024]{1to2} # AVX512{DQ,VL}
- vcvtqq2psx xmm30, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
- vcvtqq2psx xmm30, [rdx-1032]{1to2} # AVX512{DQ,VL}
+ vcvtqq2ps xmm30, QWORD PTR [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
+ vcvtqq2ps xmm30, QWORD PTR [rdx+1024]{1to2} # AVX512{DQ,VL}
+ vcvtqq2ps xmm30, QWORD PTR [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
+ vcvtqq2ps xmm30, QWORD PTR [rdx-1032]{1to2} # AVX512{DQ,VL}
vcvtqq2ps xmm30, ymm29 # AVX512{DQ,VL}
vcvtqq2ps xmm30{k7}, ymm29 # AVX512{DQ,VL}
vcvtqq2ps xmm30{k7}{z}, ymm29 # AVX512{DQ,VL}
vcvtqq2ps xmm30, YMMWORD PTR [rcx] # AVX512{DQ,VL}
vcvtqq2ps xmm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{DQ,VL}
- vcvtqq2psy xmm30, [rcx]{1to4} # AVX512{DQ,VL}
+ vcvtqq2ps xmm30, [rcx]{1to4} # AVX512{DQ,VL}
vcvtqq2ps xmm30, YMMWORD PTR [rdx+4064] # AVX512{DQ,VL} Disp8
vcvtqq2ps xmm30, YMMWORD PTR [rdx+4096] # AVX512{DQ,VL}
vcvtqq2ps xmm30, YMMWORD PTR [rdx-4096] # AVX512{DQ,VL} Disp8
vcvtqq2ps xmm30, YMMWORD PTR [rdx-4128] # AVX512{DQ,VL}
- vcvtqq2psy xmm30, [rdx+1016]{1to4} # AVX512{DQ,VL} Disp8
- vcvtqq2psy xmm30, [rdx+1024]{1to4} # AVX512{DQ,VL}
- vcvtqq2psy xmm30, [rdx-1024]{1to4} # AVX512{DQ,VL} Disp8
- vcvtqq2psy xmm30, [rdx-1032]{1to4} # AVX512{DQ,VL}
+ vcvtqq2ps xmm30, QWORD PTR [rdx+1016]{1to4} # AVX512{DQ,VL} Disp8
+ vcvtqq2ps xmm30, QWORD PTR [rdx+1024]{1to4} # AVX512{DQ,VL}
+ vcvtqq2ps xmm30, QWORD PTR [rdx-1024]{1to4} # AVX512{DQ,VL} Disp8
+ vcvtqq2ps xmm30, QWORD PTR [rdx-1032]{1to4} # AVX512{DQ,VL}
vcvtuqq2pd xmm30, xmm29 # AVX512{DQ,VL}
vcvtuqq2pd xmm30{k7}, xmm29 # AVX512{DQ,VL}
vcvtuqq2pd xmm30{k7}{z}, xmm29 # AVX512{DQ,VL}
@@ -1090,29 +1090,29 @@ _start:
vcvtuqq2ps xmm30{k7}{z}, xmm29 # AVX512{DQ,VL}
vcvtuqq2ps xmm30, XMMWORD PTR [rcx] # AVX512{DQ,VL}
vcvtuqq2ps xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{DQ,VL}
- vcvtuqq2psx xmm30, [rcx]{1to2} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm30, [rcx]{1to2} # AVX512{DQ,VL}
vcvtuqq2ps xmm30, XMMWORD PTR [rdx+2032] # AVX512{DQ,VL} Disp8
vcvtuqq2ps xmm30, XMMWORD PTR [rdx+2048] # AVX512{DQ,VL}
vcvtuqq2ps xmm30, XMMWORD PTR [rdx-2048] # AVX512{DQ,VL} Disp8
vcvtuqq2ps xmm30, XMMWORD PTR [rdx-2064] # AVX512{DQ,VL}
- vcvtuqq2psx xmm30, [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
- vcvtuqq2psx xmm30, [rdx+1024]{1to2} # AVX512{DQ,VL}
- vcvtuqq2psx xmm30, [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
- vcvtuqq2psx xmm30, [rdx-1032]{1to2} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm30, QWORD PTR [rdx+1016]{1to2} # AVX512{DQ,VL} Disp8
+ vcvtuqq2ps xmm30, QWORD PTR [rdx+1024]{1to2} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm30, QWORD PTR [rdx-1024]{1to2} # AVX512{DQ,VL} Disp8
+ vcvtuqq2ps xmm30, QWORD PTR [rdx-1032]{1to2} # AVX512{DQ,VL}
vcvtuqq2ps xmm30, ymm29 # AVX512{DQ,VL}
vcvtuqq2ps xmm30{k7}, ymm29 # AVX512{DQ,VL}
vcvtuqq2ps xmm30{k7}{z}, ymm29 # AVX512{DQ,VL}
vcvtuqq2ps xmm30, YMMWORD PTR [rcx] # AVX512{DQ,VL}
vcvtuqq2ps xmm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{DQ,VL}
- vcvtuqq2psy xmm30, [rcx]{1to4} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm30, [rcx]{1to4} # AVX512{DQ,VL}
vcvtuqq2ps xmm30, YMMWORD PTR [rdx+4064] # AVX512{DQ,VL} Disp8
vcvtuqq2ps xmm30, YMMWORD PTR [rdx+4096] # AVX512{DQ,VL}
vcvtuqq2ps xmm30, YMMWORD PTR [rdx-4096] # AVX512{DQ,VL} Disp8
vcvtuqq2ps xmm30, YMMWORD PTR [rdx-4128] # AVX512{DQ,VL}
- vcvtuqq2psy xmm30, [rdx+1016]{1to4} # AVX512{DQ,VL} Disp8
- vcvtuqq2psy xmm30, [rdx+1024]{1to4} # AVX512{DQ,VL}
- vcvtuqq2psy xmm30, [rdx-1024]{1to4} # AVX512{DQ,VL} Disp8
- vcvtuqq2psy xmm30, [rdx-1032]{1to4} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm30, QWORD PTR [rdx+1016]{1to4} # AVX512{DQ,VL} Disp8
+ vcvtuqq2ps xmm30, QWORD PTR [rdx+1024]{1to4} # AVX512{DQ,VL}
+ vcvtuqq2ps xmm30, QWORD PTR [rdx-1024]{1to4} # AVX512{DQ,VL} Disp8
+ vcvtuqq2ps xmm30, QWORD PTR [rdx-1032]{1to4} # AVX512{DQ,VL}
vextractf64x2 xmm30, ymm29, 0xab # AVX512{DQ,VL}
vextractf64x2 xmm30{k7}, ymm29, 0xab # AVX512{DQ,VL}
vextractf64x2 xmm30{k7}{z}, ymm29, 0xab # AVX512{DQ,VL}
@@ -1126,57 +1126,57 @@ _start:
vfpclasspd k5, xmm30, 123 # AVX512{DQ,VL}
vfpclasspd k5, XMMWORD PTR [rcx], 123 # AVX512{DQ,VL}
vfpclasspd k5, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512{DQ,VL}
- vfpclasspdx k5, [rcx]{1to2}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5, [rcx]{1to2}, 123 # AVX512{DQ,VL}
vfpclasspd k5, XMMWORD PTR [rdx+2032], 123 # AVX512{DQ,VL} Disp8
vfpclasspd k5, XMMWORD PTR [rdx+2048], 123 # AVX512{DQ,VL}
vfpclasspd k5, XMMWORD PTR [rdx-2048], 123 # AVX512{DQ,VL} Disp8
vfpclasspd k5, XMMWORD PTR [rdx-2064], 123 # AVX512{DQ,VL}
- vfpclasspdx k5, [rdx+1016]{1to2}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspdx k5, [rdx+1024]{1to2}, 123 # AVX512{DQ,VL}
- vfpclasspdx k5, [rdx-1024]{1to2}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspdx k5, [rdx-1032]{1to2}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5, QWORD PTR [rdx+1016]{1to2}, 123 # AVX512{DQ,VL} Disp8
+ vfpclasspd k5, QWORD PTR [rdx+1024]{1to2}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5, QWORD PTR [rdx-1024]{1to2}, 123 # AVX512{DQ,VL} Disp8
+ vfpclasspd k5, QWORD PTR [rdx-1032]{1to2}, 123 # AVX512{DQ,VL}
vfpclasspd k5, ymm30, 0xab # AVX512{DQ,VL}
vfpclasspd k5{k7}, ymm30, 0xab # AVX512{DQ,VL}
vfpclasspd k5, ymm30, 123 # AVX512{DQ,VL}
vfpclasspd k5, YMMWORD PTR [rcx], 123 # AVX512{DQ,VL}
vfpclasspd k5, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512{DQ,VL}
- vfpclasspdy k5, [rcx]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5, [rcx]{1to4}, 123 # AVX512{DQ,VL}
vfpclasspd k5, YMMWORD PTR [rdx+4064], 123 # AVX512{DQ,VL} Disp8
vfpclasspd k5, YMMWORD PTR [rdx+4096], 123 # AVX512{DQ,VL}
vfpclasspd k5, YMMWORD PTR [rdx-4096], 123 # AVX512{DQ,VL} Disp8
vfpclasspd k5, YMMWORD PTR [rdx-4128], 123 # AVX512{DQ,VL}
- vfpclasspdy k5, [rdx+1016]{1to4}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspdy k5, [rdx+1024]{1to4}, 123 # AVX512{DQ,VL}
- vfpclasspdy k5, [rdx-1024]{1to4}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspdy k5, [rdx-1032]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5, QWORD PTR [rdx+1016]{1to4}, 123 # AVX512{DQ,VL} Disp8
+ vfpclasspd k5, QWORD PTR [rdx+1024]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclasspd k5, QWORD PTR [rdx-1024]{1to4}, 123 # AVX512{DQ,VL} Disp8
+ vfpclasspd k5, QWORD PTR [rdx-1032]{1to4}, 123 # AVX512{DQ,VL}
vfpclassps k5, xmm30, 0xab # AVX512{DQ,VL}
vfpclassps k5{k7}, xmm30, 0xab # AVX512{DQ,VL}
vfpclassps k5, xmm30, 123 # AVX512{DQ,VL}
vfpclassps k5, XMMWORD PTR [rcx], 123 # AVX512{DQ,VL}
vfpclassps k5, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512{DQ,VL}
- vfpclasspsx k5, [rcx]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclassps k5, [rcx]{1to4}, 123 # AVX512{DQ,VL}
vfpclassps k5, XMMWORD PTR [rdx+2032], 123 # AVX512{DQ,VL} Disp8
vfpclassps k5, XMMWORD PTR [rdx+2048], 123 # AVX512{DQ,VL}
vfpclassps k5, XMMWORD PTR [rdx-2048], 123 # AVX512{DQ,VL} Disp8
vfpclassps k5, XMMWORD PTR [rdx-2064], 123 # AVX512{DQ,VL}
- vfpclasspsx k5, [rdx+508]{1to4}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspsx k5, [rdx+512]{1to4}, 123 # AVX512{DQ,VL}
- vfpclasspsx k5, [rdx-512]{1to4}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspsx k5, [rdx-516]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclassps k5, DWORD PTR [rdx+508]{1to4}, 123 # AVX512{DQ,VL} Disp8
+ vfpclassps k5, DWORD PTR [rdx+512]{1to4}, 123 # AVX512{DQ,VL}
+ vfpclassps k5, DWORD PTR [rdx-512]{1to4}, 123 # AVX512{DQ,VL} Disp8
+ vfpclassps k5, DWORD PTR [rdx-516]{1to4}, 123 # AVX512{DQ,VL}
vfpclassps k5, ymm30, 0xab # AVX512{DQ,VL}
vfpclassps k5{k7}, ymm30, 0xab # AVX512{DQ,VL}
vfpclassps k5, ymm30, 123 # AVX512{DQ,VL}
vfpclassps k5, YMMWORD PTR [rcx], 123 # AVX512{DQ,VL}
vfpclassps k5, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512{DQ,VL}
- vfpclasspsy k5, [rcx]{1to8}, 123 # AVX512{DQ,VL}
+ vfpclassps k5, [rcx]{1to8}, 123 # AVX512{DQ,VL}
vfpclassps k5, YMMWORD PTR [rdx+4064], 123 # AVX512{DQ,VL} Disp8
vfpclassps k5, YMMWORD PTR [rdx+4096], 123 # AVX512{DQ,VL}
vfpclassps k5, YMMWORD PTR [rdx-4096], 123 # AVX512{DQ,VL} Disp8
vfpclassps k5, YMMWORD PTR [rdx-4128], 123 # AVX512{DQ,VL}
- vfpclasspsy k5, [rdx+508]{1to8}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspsy k5, [rdx+512]{1to8}, 123 # AVX512{DQ,VL}
- vfpclasspsy k5, [rdx-512]{1to8}, 123 # AVX512{DQ,VL} Disp8
- vfpclasspsy k5, [rdx-516]{1to8}, 123 # AVX512{DQ,VL}
+ vfpclassps k5, DWORD PTR [rdx+508]{1to8}, 123 # AVX512{DQ,VL} Disp8
+ vfpclassps k5, DWORD PTR [rdx+512]{1to8}, 123 # AVX512{DQ,VL}
+ vfpclassps k5, DWORD PTR [rdx-512]{1to8}, 123 # AVX512{DQ,VL} Disp8
+ vfpclassps k5, DWORD PTR [rdx-516]{1to8}, 123 # AVX512{DQ,VL}
vinsertf64x2 ymm30, ymm29, xmm28, 0xab # AVX512{DQ,VL}
vinsertf64x2 ymm30{k7}, ymm29, xmm28, 0xab # AVX512{DQ,VL}
vinsertf64x2 ymm30{k7}{z}, ymm29, xmm28, 0xab # AVX512{DQ,VL}
--- 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512f_vl.s
+++ 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512f_vl.s
@@ -351,7 +351,7 @@ _start:
vcvtpd2dq %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vcvtpd2dqx (%rcx), %xmm30 # AVX512{F,VL}
vcvtpd2dqx 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
- vcvtpd2dqx (%rcx){1to2}, %xmm30 # AVX512{F,VL}
+ vcvtpd2dq (%rcx){1to2}, %xmm30 # AVX512{F,VL}
vcvtpd2dqx 2032(%rdx), %xmm30 # AVX512{F,VL} Disp8
vcvtpd2dqx 2048(%rdx), %xmm30 # AVX512{F,VL}
vcvtpd2dqx -2048(%rdx), %xmm30 # AVX512{F,VL} Disp8
@@ -365,7 +365,7 @@ _start:
vcvtpd2dq %ymm29, %xmm30{%k7}{z} # AVX512{F,VL}
vcvtpd2dqy (%rcx), %xmm30 # AVX512{F,VL}
vcvtpd2dqy 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
- vcvtpd2dqy (%rcx){1to4}, %xmm30 # AVX512{F,VL}
+ vcvtpd2dq (%rcx){1to4}, %xmm30 # AVX512{F,VL}
vcvtpd2dqy 4064(%rdx), %xmm30 # AVX512{F,VL} Disp8
vcvtpd2dqy 4096(%rdx), %xmm30 # AVX512{F,VL}
vcvtpd2dqy -4096(%rdx), %xmm30 # AVX512{F,VL} Disp8
@@ -379,7 +379,7 @@ _start:
vcvtpd2ps %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vcvtpd2psx (%rcx), %xmm30 # AVX512{F,VL}
vcvtpd2psx 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
- vcvtpd2psx (%rcx){1to2}, %xmm30 # AVX512{F,VL}
+ vcvtpd2ps (%rcx){1to2}, %xmm30 # AVX512{F,VL}
vcvtpd2psx 2032(%rdx), %xmm30 # AVX512{F,VL} Disp8
vcvtpd2psx 2048(%rdx), %xmm30 # AVX512{F,VL}
vcvtpd2psx -2048(%rdx), %xmm30 # AVX512{F,VL} Disp8
@@ -393,7 +393,7 @@ _start:
vcvtpd2ps %ymm29, %xmm30{%k7}{z} # AVX512{F,VL}
vcvtpd2psy (%rcx), %xmm30 # AVX512{F,VL}
vcvtpd2psy 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
- vcvtpd2psy (%rcx){1to4}, %xmm30 # AVX512{F,VL}
+ vcvtpd2ps (%rcx){1to4}, %xmm30 # AVX512{F,VL}
vcvtpd2psy 4064(%rdx), %xmm30 # AVX512{F,VL} Disp8
vcvtpd2psy 4096(%rdx), %xmm30 # AVX512{F,VL}
vcvtpd2psy -4096(%rdx), %xmm30 # AVX512{F,VL} Disp8
@@ -407,7 +407,7 @@ _start:
vcvtpd2udq %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vcvtpd2udqx (%rcx), %xmm30 # AVX512{F,VL}
vcvtpd2udqx 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
- vcvtpd2udqx (%rcx){1to2}, %xmm30 # AVX512{F,VL}
+ vcvtpd2udq (%rcx){1to2}, %xmm30 # AVX512{F,VL}
vcvtpd2udqx 2032(%rdx), %xmm30 # AVX512{F,VL} Disp8
vcvtpd2udqx 2048(%rdx), %xmm30 # AVX512{F,VL}
vcvtpd2udqx -2048(%rdx), %xmm30 # AVX512{F,VL} Disp8
@@ -421,7 +421,7 @@ _start:
vcvtpd2udq %ymm29, %xmm30{%k7}{z} # AVX512{F,VL}
vcvtpd2udqy (%rcx), %xmm30 # AVX512{F,VL}
vcvtpd2udqy 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
- vcvtpd2udqy (%rcx){1to4}, %xmm30 # AVX512{F,VL}
+ vcvtpd2udq (%rcx){1to4}, %xmm30 # AVX512{F,VL}
vcvtpd2udqy 4064(%rdx), %xmm30 # AVX512{F,VL} Disp8
vcvtpd2udqy 4096(%rdx), %xmm30 # AVX512{F,VL}
vcvtpd2udqy -4096(%rdx), %xmm30 # AVX512{F,VL} Disp8
@@ -545,7 +545,7 @@ _start:
vcvttpd2dq %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vcvttpd2dqx (%rcx), %xmm30 # AVX512{F,VL}
vcvttpd2dqx 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
- vcvttpd2dqx (%rcx){1to2}, %xmm30 # AVX512{F,VL}
+ vcvttpd2dq (%rcx){1to2}, %xmm30 # AVX512{F,VL}
vcvttpd2dqx 2032(%rdx), %xmm30 # AVX512{F,VL} Disp8
vcvttpd2dqx 2048(%rdx), %xmm30 # AVX512{F,VL}
vcvttpd2dqx -2048(%rdx), %xmm30 # AVX512{F,VL} Disp8
@@ -559,7 +559,7 @@ _start:
vcvttpd2dq %ymm29, %xmm30{%k7}{z} # AVX512{F,VL}
vcvttpd2dqy (%rcx), %xmm30 # AVX512{F,VL}
vcvttpd2dqy 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
- vcvttpd2dqy (%rcx){1to4}, %xmm30 # AVX512{F,VL}
+ vcvttpd2dq (%rcx){1to4}, %xmm30 # AVX512{F,VL}
vcvttpd2dqy 4064(%rdx), %xmm30 # AVX512{F,VL} Disp8
vcvttpd2dqy 4096(%rdx), %xmm30 # AVX512{F,VL}
vcvttpd2dqy -4096(%rdx), %xmm30 # AVX512{F,VL} Disp8
@@ -6660,85 +6660,85 @@ _start:
vcvtpd2dq xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vcvtpd2dq xmm30, XMMWORD PTR [rcx] # AVX512{F,VL}
vcvtpd2dq xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
- vcvtpd2dqx xmm30, [rcx]{1to2} # AVX512{F,VL}
+ vcvtpd2dq xmm30, [rcx]{1to2} # AVX512{F,VL}
vcvtpd2dq xmm30, XMMWORD PTR [rdx+2032] # AVX512{F,VL} Disp8
vcvtpd2dq xmm30, XMMWORD PTR [rdx+2048] # AVX512{F,VL}
vcvtpd2dq xmm30, XMMWORD PTR [rdx-2048] # AVX512{F,VL} Disp8
vcvtpd2dq xmm30, XMMWORD PTR [rdx-2064] # AVX512{F,VL}
- vcvtpd2dqx xmm30, [rdx+1016]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2dqx xmm30, [rdx+1024]{1to2} # AVX512{F,VL}
- vcvtpd2dqx xmm30, [rdx-1024]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2dqx xmm30, [rdx-1032]{1to2} # AVX512{F,VL}
+ vcvtpd2dq xmm30, QWORD PTR [rdx+1016]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2dq xmm30, QWORD PTR [rdx+1024]{1to2} # AVX512{F,VL}
+ vcvtpd2dq xmm30, QWORD PTR [rdx-1024]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2dq xmm30, QWORD PTR [rdx-1032]{1to2} # AVX512{F,VL}
vcvtpd2dq xmm30, ymm29 # AVX512{F,VL}
vcvtpd2dq xmm30{k7}, ymm29 # AVX512{F,VL}
vcvtpd2dq xmm30{k7}{z}, ymm29 # AVX512{F,VL}
vcvtpd2dq xmm30, YMMWORD PTR [rcx] # AVX512{F,VL}
vcvtpd2dq xmm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
- vcvtpd2dqy xmm30, [rcx]{1to4} # AVX512{F,VL}
+ vcvtpd2dq xmm30, [rcx]{1to4} # AVX512{F,VL}
vcvtpd2dq xmm30, YMMWORD PTR [rdx+4064] # AVX512{F,VL} Disp8
vcvtpd2dq xmm30, YMMWORD PTR [rdx+4096] # AVX512{F,VL}
vcvtpd2dq xmm30, YMMWORD PTR [rdx-4096] # AVX512{F,VL} Disp8
vcvtpd2dq xmm30, YMMWORD PTR [rdx-4128] # AVX512{F,VL}
- vcvtpd2dqy xmm30, [rdx+1016]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2dqy xmm30, [rdx+1024]{1to4} # AVX512{F,VL}
- vcvtpd2dqy xmm30, [rdx-1024]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2dqy xmm30, [rdx-1032]{1to4} # AVX512{F,VL}
+ vcvtpd2dq xmm30, QWORD PTR [rdx+1016]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2dq xmm30, QWORD PTR [rdx+1024]{1to4} # AVX512{F,VL}
+ vcvtpd2dq xmm30, QWORD PTR [rdx-1024]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2dq xmm30, QWORD PTR [rdx-1032]{1to4} # AVX512{F,VL}
vcvtpd2ps xmm30, xmm29 # AVX512{F,VL}
vcvtpd2ps xmm30{k7}, xmm29 # AVX512{F,VL}
vcvtpd2ps xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vcvtpd2ps xmm30, XMMWORD PTR [rcx] # AVX512{F,VL}
vcvtpd2ps xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
- vcvtpd2psx xmm30, [rcx]{1to2} # AVX512{F,VL}
+ vcvtpd2ps xmm30, [rcx]{1to2} # AVX512{F,VL}
vcvtpd2ps xmm30, XMMWORD PTR [rdx+2032] # AVX512{F,VL} Disp8
vcvtpd2ps xmm30, XMMWORD PTR [rdx+2048] # AVX512{F,VL}
vcvtpd2ps xmm30, XMMWORD PTR [rdx-2048] # AVX512{F,VL} Disp8
vcvtpd2ps xmm30, XMMWORD PTR [rdx-2064] # AVX512{F,VL}
- vcvtpd2psx xmm30, [rdx+1016]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2psx xmm30, [rdx+1024]{1to2} # AVX512{F,VL}
- vcvtpd2psx xmm30, [rdx-1024]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2psx xmm30, [rdx-1032]{1to2} # AVX512{F,VL}
+ vcvtpd2ps xmm30, QWORD PTR [rdx+1016]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2ps xmm30, QWORD PTR [rdx+1024]{1to2} # AVX512{F,VL}
+ vcvtpd2ps xmm30, QWORD PTR [rdx-1024]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2ps xmm30, QWORD PTR [rdx-1032]{1to2} # AVX512{F,VL}
vcvtpd2ps xmm30, ymm29 # AVX512{F,VL}
vcvtpd2ps xmm30{k7}, ymm29 # AVX512{F,VL}
vcvtpd2ps xmm30{k7}{z}, ymm29 # AVX512{F,VL}
vcvtpd2ps xmm30, YMMWORD PTR [rcx] # AVX512{F,VL}
vcvtpd2ps xmm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
- vcvtpd2psy xmm30, [rcx]{1to4} # AVX512{F,VL}
+ vcvtpd2ps xmm30, [rcx]{1to4} # AVX512{F,VL}
vcvtpd2ps xmm30, YMMWORD PTR [rdx+4064] # AVX512{F,VL} Disp8
vcvtpd2ps xmm30, YMMWORD PTR [rdx+4096] # AVX512{F,VL}
vcvtpd2ps xmm30, YMMWORD PTR [rdx-4096] # AVX512{F,VL} Disp8
vcvtpd2ps xmm30, YMMWORD PTR [rdx-4128] # AVX512{F,VL}
- vcvtpd2psy xmm30, [rdx+1016]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2psy xmm30, [rdx+1024]{1to4} # AVX512{F,VL}
- vcvtpd2psy xmm30, [rdx-1024]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2psy xmm30, [rdx-1032]{1to4} # AVX512{F,VL}
+ vcvtpd2ps xmm30, QWORD PTR [rdx+1016]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2ps xmm30, QWORD PTR [rdx+1024]{1to4} # AVX512{F,VL}
+ vcvtpd2ps xmm30, QWORD PTR [rdx-1024]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2ps xmm30, QWORD PTR [rdx-1032]{1to4} # AVX512{F,VL}
vcvtpd2udq xmm30, xmm29 # AVX512{F,VL}
vcvtpd2udq xmm30{k7}, xmm29 # AVX512{F,VL}
vcvtpd2udq xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vcvtpd2udq xmm30, XMMWORD PTR [rcx] # AVX512{F,VL}
vcvtpd2udq xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
- vcvtpd2udqx xmm30, [rcx]{1to2} # AVX512{F,VL}
+ vcvtpd2udq xmm30, [rcx]{1to2} # AVX512{F,VL}
vcvtpd2udq xmm30, XMMWORD PTR [rdx+2032] # AVX512{F,VL} Disp8
vcvtpd2udq xmm30, XMMWORD PTR [rdx+2048] # AVX512{F,VL}
vcvtpd2udq xmm30, XMMWORD PTR [rdx-2048] # AVX512{F,VL} Disp8
vcvtpd2udq xmm30, XMMWORD PTR [rdx-2064] # AVX512{F,VL}
- vcvtpd2udqx xmm30, [rdx+1016]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2udqx xmm30, [rdx+1024]{1to2} # AVX512{F,VL}
- vcvtpd2udqx xmm30, [rdx-1024]{1to2} # AVX512{F,VL} Disp8
- vcvtpd2udqx xmm30, [rdx-1032]{1to2} # AVX512{F,VL}
+ vcvtpd2udq xmm30, QWORD PTR [rdx+1016]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2udq xmm30, QWORD PTR [rdx+1024]{1to2} # AVX512{F,VL}
+ vcvtpd2udq xmm30, QWORD PTR [rdx-1024]{1to2} # AVX512{F,VL} Disp8
+ vcvtpd2udq xmm30, QWORD PTR [rdx-1032]{1to2} # AVX512{F,VL}
vcvtpd2udq xmm30, ymm29 # AVX512{F,VL}
vcvtpd2udq xmm30{k7}, ymm29 # AVX512{F,VL}
vcvtpd2udq xmm30{k7}{z}, ymm29 # AVX512{F,VL}
vcvtpd2udq xmm30, YMMWORD PTR [rcx] # AVX512{F,VL}
vcvtpd2udq xmm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
- vcvtpd2udqy xmm30, [rcx]{1to4} # AVX512{F,VL}
+ vcvtpd2udq xmm30, [rcx]{1to4} # AVX512{F,VL}
vcvtpd2udq xmm30, YMMWORD PTR [rdx+4064] # AVX512{F,VL} Disp8
vcvtpd2udq xmm30, YMMWORD PTR [rdx+4096] # AVX512{F,VL}
vcvtpd2udq xmm30, YMMWORD PTR [rdx-4096] # AVX512{F,VL} Disp8
vcvtpd2udq xmm30, YMMWORD PTR [rdx-4128] # AVX512{F,VL}
- vcvtpd2udqy xmm30, [rdx+1016]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2udqy xmm30, [rdx+1024]{1to4} # AVX512{F,VL}
- vcvtpd2udqy xmm30, [rdx-1024]{1to4} # AVX512{F,VL} Disp8
- vcvtpd2udqy xmm30, [rdx-1032]{1to4} # AVX512{F,VL}
+ vcvtpd2udq xmm30, QWORD PTR [rdx+1016]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2udq xmm30, QWORD PTR [rdx+1024]{1to4} # AVX512{F,VL}
+ vcvtpd2udq xmm30, QWORD PTR [rdx-1024]{1to4} # AVX512{F,VL} Disp8
+ vcvtpd2udq xmm30, QWORD PTR [rdx-1032]{1to4} # AVX512{F,VL}
vcvtph2ps xmm30, xmm29 # AVX512{F,VL}
vcvtph2ps xmm30{k7}, xmm29 # AVX512{F,VL}
vcvtph2ps xmm30{k7}{z}, xmm29 # AVX512{F,VL}
@@ -6854,29 +6854,29 @@ _start:
vcvttpd2dq xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vcvttpd2dq xmm30, XMMWORD PTR [rcx] # AVX512{F,VL}
vcvttpd2dq xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
- vcvttpd2dqx xmm30, [rcx]{1to2} # AVX512{F,VL}
+ vcvttpd2dq xmm30, [rcx]{1to2} # AVX512{F,VL}
vcvttpd2dq xmm30, XMMWORD PTR [rdx+2032] # AVX512{F,VL} Disp8
vcvttpd2dq xmm30, XMMWORD PTR [rdx+2048] # AVX512{F,VL}
vcvttpd2dq xmm30, XMMWORD PTR [rdx-2048] # AVX512{F,VL} Disp8
vcvttpd2dq xmm30, XMMWORD PTR [rdx-2064] # AVX512{F,VL}
- vcvttpd2dqx xmm30, [rdx+1016]{1to2} # AVX512{F,VL} Disp8
- vcvttpd2dqx xmm30, [rdx+1024]{1to2} # AVX512{F,VL}
- vcvttpd2dqx xmm30, [rdx-1024]{1to2} # AVX512{F,VL} Disp8
- vcvttpd2dqx xmm30, [rdx-1032]{1to2} # AVX512{F,VL}
+ vcvttpd2dq xmm30, QWORD PTR [rdx+1016]{1to2} # AVX512{F,VL} Disp8
+ vcvttpd2dq xmm30, QWORD PTR [rdx+1024]{1to2} # AVX512{F,VL}
+ vcvttpd2dq xmm30, QWORD PTR [rdx-1024]{1to2} # AVX512{F,VL} Disp8
+ vcvttpd2dq xmm30, QWORD PTR [rdx-1032]{1to2} # AVX512{F,VL}
vcvttpd2dq xmm30, ymm29 # AVX512{F,VL}
vcvttpd2dq xmm30{k7}, ymm29 # AVX512{F,VL}
vcvttpd2dq xmm30{k7}{z}, ymm29 # AVX512{F,VL}
vcvttpd2dq xmm30, YMMWORD PTR [rcx] # AVX512{F,VL}
vcvttpd2dq xmm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
- vcvttpd2dqy xmm30, [rcx]{1to4} # AVX512{F,VL}
+ vcvttpd2dq xmm30, [rcx]{1to4} # AVX512{F,VL}
vcvttpd2dq xmm30, YMMWORD PTR [rdx+4064] # AVX512{F,VL} Disp8
vcvttpd2dq xmm30, YMMWORD PTR [rdx+4096] # AVX512{F,VL}
vcvttpd2dq xmm30, YMMWORD PTR [rdx-4096] # AVX512{F,VL} Disp8
vcvttpd2dq xmm30, YMMWORD PTR [rdx-4128] # AVX512{F,VL}
- vcvttpd2dqy xmm30, [rdx+1016]{1to4} # AVX512{F,VL} Disp8
- vcvttpd2dqy xmm30, [rdx+1024]{1to4} # AVX512{F,VL}
- vcvttpd2dqy xmm30, [rdx-1024]{1to4} # AVX512{F,VL} Disp8
- vcvttpd2dqy xmm30, [rdx-1032]{1to4} # AVX512{F,VL}
+ vcvttpd2dq xmm30, QWORD PTR [rdx+1016]{1to4} # AVX512{F,VL} Disp8
+ vcvttpd2dq xmm30, QWORD PTR [rdx+1024]{1to4} # AVX512{F,VL}
+ vcvttpd2dq xmm30, QWORD PTR [rdx-1024]{1to4} # AVX512{F,VL} Disp8
+ vcvttpd2dq xmm30, QWORD PTR [rdx-1032]{1to4} # AVX512{F,VL}
vcvttps2dq xmm30, xmm29 # AVX512{F,VL}
vcvttps2dq xmm30{k7}, xmm29 # AVX512{F,VL}
vcvttps2dq xmm30{k7}{z}, xmm29 # AVX512{F,VL}
@@ -12404,29 +12404,29 @@ _start:
vcvttpd2udq xmm30{k7}{z}, xmm29 # AVX512{F,VL}
vcvttpd2udq xmm30, XMMWORD PTR [rcx] # AVX512{F,VL}
vcvttpd2udq xmm30, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
- vcvttpd2udqx xmm30, [rcx]{1to2} # AVX512{F,VL}
+ vcvttpd2udq xmm30, [rcx]{1to2} # AVX512{F,VL}
vcvttpd2udq xmm30, XMMWORD PTR [rdx+2032] # AVX512{F,VL} Disp8
vcvttpd2udq xmm30, XMMWORD PTR [rdx+2048] # AVX512{F,VL}
vcvttpd2udq xmm30, XMMWORD PTR [rdx-2048] # AVX512{F,VL} Disp8
vcvttpd2udq xmm30, XMMWORD PTR [rdx-2064] # AVX512{F,VL}
- vcvttpd2udqx xmm30, [rdx+1016]{1to2} # AVX512{F,VL} Disp8
- vcvttpd2udqx xmm30, [rdx+1024]{1to2} # AVX512{F,VL}
- vcvttpd2udqx xmm30, [rdx-1024]{1to2} # AVX512{F,VL} Disp8
- vcvttpd2udqx xmm30, [rdx-1032]{1to2} # AVX512{F,VL}
+ vcvttpd2udq xmm30, QWORD PTR [rdx+1016]{1to2} # AVX512{F,VL} Disp8
+ vcvttpd2udq xmm30, QWORD PTR [rdx+1024]{1to2} # AVX512{F,VL}
+ vcvttpd2udq xmm30, QWORD PTR [rdx-1024]{1to2} # AVX512{F,VL} Disp8
+ vcvttpd2udq xmm30, QWORD PTR [rdx-1032]{1to2} # AVX512{F,VL}
vcvttpd2udq xmm30, ymm29 # AVX512{F,VL}
vcvttpd2udq xmm30{k7}, ymm29 # AVX512{F,VL}
vcvttpd2udq xmm30{k7}{z}, ymm29 # AVX512{F,VL}
vcvttpd2udq xmm30, YMMWORD PTR [rcx] # AVX512{F,VL}
vcvttpd2udq xmm30, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{F,VL}
- vcvttpd2udqy xmm30, [rcx]{1to4} # AVX512{F,VL}
+ vcvttpd2udq xmm30, [rcx]{1to4} # AVX512{F,VL}
vcvttpd2udq xmm30, YMMWORD PTR [rdx+4064] # AVX512{F,VL} Disp8
vcvttpd2udq xmm30, YMMWORD PTR [rdx+4096] # AVX512{F,VL}
vcvttpd2udq xmm30, YMMWORD PTR [rdx-4096] # AVX512{F,VL} Disp8
vcvttpd2udq xmm30, YMMWORD PTR [rdx-4128] # AVX512{F,VL}
- vcvttpd2udqy xmm30, [rdx+1016]{1to4} # AVX512{F,VL} Disp8
- vcvttpd2udqy xmm30, [rdx+1024]{1to4} # AVX512{F,VL}
- vcvttpd2udqy xmm30, [rdx-1024]{1to4} # AVX512{F,VL} Disp8
- vcvttpd2udqy xmm30, [rdx-1032]{1to4} # AVX512{F,VL}
+ vcvttpd2udq xmm30, QWORD PTR [rdx+1016]{1to4} # AVX512{F,VL} Disp8
+ vcvttpd2udq xmm30, QWORD PTR [rdx+1024]{1to4} # AVX512{F,VL}
+ vcvttpd2udq xmm30, QWORD PTR [rdx-1024]{1to4} # AVX512{F,VL} Disp8
+ vcvttpd2udq xmm30, QWORD PTR [rdx-1032]{1to4} # AVX512{F,VL}
vcvttps2udq xmm30, xmm29 # AVX512{F,VL}
vcvttps2udq xmm30{k7}, xmm29 # AVX512{F,VL}
vcvttps2udq xmm30{k7}{z}, xmm29 # AVX512{F,VL}
Attachment:
binutils-master-x86-AVX512-bcst-disambiguates.patch
Description: Text document
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