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[PATCH 1/2][Aarch64][binutils] Add support for ARMv8.1a Limited Ordering Regions extension
- From: Matthew Wahab <matthew dot wahab at arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Wed, 20 May 2015 15:40:12 +0100
- Subject: [PATCH 1/2][Aarch64][binutils] Add support for ARMv8.1a Limited Ordering Regions extension
- Authentication-results: sourceware.org; auth=none
ARMv8.1a introduces an optional architectural extension called Limited Ordering
Regions which adds new variants of the load-acquire and store-release
instructions. This patch adds support for these instructions, a following patch
will add support in gas.
Tested aarch64-none-linux-gnu with check-gas and check-binutils.
Ok for trunk?
Matthew
include/
2015-05-20 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_LOR): New.
opcodes/
2015-05-20 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-tbl.h (aarch64_feature_lor): New.
(LOR): New.
(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
"stllrb", "stllrh".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 7130d2d..8711347 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -39,6 +39,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
+#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 228ce35..0e43914 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1222,6 +1222,8 @@ static const aarch64_feature_set aarch64_feature_crc =
AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
static const aarch64_feature_set aarch64_feature_lse =
AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0);
+static const aarch64_feature_set aarch64_feature_lor =
+ AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -1229,6 +1231,7 @@ static const aarch64_feature_set aarch64_feature_lse =
#define CRYPTO &aarch64_feature_crypto
#define CRC &aarch64_feature_crc
#define LSE &aarch64_feature_lse
+#define LOR &aarch64_feature_lor
struct aarch64_opcode aarch64_opcode_table[] =
{
@@ -2017,6 +2020,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
{"stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
{"ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
+ /* Limited Ordering Regions load/store instructions. */
+ {"ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
+ {"ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"stllr", 0x889f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
+ {"stllrb", 0x089f7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
+ {"stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
/* Load/store no-allocate pair (offset). */
{"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
{"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},