This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[Patch:RL78]: Incorrect disassembler output generated by "objdump" for index addressing using DE register.
- From: "Vinay Kumar. G" <Vinay dot G at kpit dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: "nickc at redhat dot com" <nickc at redhat dot com>
- Date: Fri, 26 Jun 2015 11:31:01 +0000
- Subject: [Patch:RL78]: Incorrect disassembler output generated by "objdump" for index addressing using DE register.
- Authentication-results: sourceware.org; auth=none
- Authentication-results: redhat.com; dkim=none (message not signed) header.d=none;
Hi,
The RL78 toolchain does not generate correct instructions with below
testcase. The instruction generation in the list file is as expected.
However, the objdump shows incorrect disassembly being generated.
For index addressing instructions the list file displays "a, [de+0]",
while the object dump shows only "a, [de]" -> Here is "+ 0" is
omitted by the toolchain.
Below testcase is for 'mov' and 'movw' instructions. Similar
behaviour is also observed with 'xch' instruction.
For example:
/* test.s */
.text
mov a, [de]
mov a, [de + 0]
mov a, [de + 1]
mov [de], a
mov [de + 0], a
mov [de + 1], a
movw ax, [de]
movw ax, [de + 0]
movw ax, [de + 1]
.end
$rl78-elf-as test.s -o test.o -aln=test.lst
$rl78-elf-objdump -d test.o
00000000 <.text>:
0: 89 mov a, [de]
1: 8a 00 mov a, [de] ---> expected "mov a, [de+0]"
3: 8a 01 mov a, [de+1]
5: 99 mov [de], a
6: 9a 00 mov [de], a ---> expected "mov [de+0], a"
8: 9a 01 mov [de+1], a
a: a9 movw ax, [de]
b: aa 00 movw ax, [de] ---> expected "movw ax, [de+0]"
d: aa 01 movw ax, [de+1]
Please review below patch and commit the same if OK.
Best Regards,
Vinay
/*******************************************************************/
opcodes/ChangeLog
2015-06-26 Vinay <Vinay.G@kpit.com>
* rl78-decode.opc (MOV): Added offset to DE
register in index addressing mode.
* rl78-decode.c: Regenerate.
--- opcodes/rl78-decode.opc.orgv 2015-04-02 10:49:08.505816687 +0530
+++ opcodes/rl78-decode.opc 2015-04-02 10:59:51.121778696 +0530
@@ -613,10 +613,10 @@
/** 1001 1001 mov %e0, %1 */
ID(mov); DM(DE, 0); SR(A);
-/** 1100 1010 mov %e0, #%1 */
+/** 1100 1010 mov %ea0, #%1 */
ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
-/** 1001 1010 mov %e0, %1 */
+/** 1001 1010 mov %ea0, %1 */
ID(mov); DM(DE, IMMU(1)); SR(A);
/** 1001 1011 mov %e0, %1 */
@@ -646,7 +646,7 @@
/** 1000 1001 mov %0, %e1 */
ID(mov); DR(A); SM(DE, 0);
-/** 1000 1010 mov %0, %e1 */
+/** 1000 1010 mov %0, %ea1 */
ID(mov); DR(A); SM(DE, IMMU(1));
/** 1000 1011 mov %0, %e1 */
@@ -817,7 +817,7 @@
/** 1011 1001 movw %e0, %1 */
ID(mov); W(); DM(DE, 0); SR(AX);
-/** 1011 1010 movw %e0, %1 */
+/** 1011 1010 movw %ea0, %1 */
ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
/** 1011 1011 movw %e0, %1 */
@@ -836,7 +836,7 @@
/** 1010 1001 movw %0, %e1 */
ID(mov); W(); DR(AX); SM(DE, 0);
-/** 1010 1010 movw %0, %e1 */
+/** 1010 1010 movw %0, %ea1 */
ID(mov); W(); DR(AX); SM(DE, IMMU(1));
/** 1010 1011 movw %0, %e1 */
@@ -1204,7 +1204,7 @@
/** 0110 0001 1010 1110 xch %0, %e1 */
ID(xch); DR(A); SM(DE, 0);
-/** 0110 0001 1010 1111 xch %0, %e1 */
+/** 0110 0001 1010 1111 xch %0, %ea1 */
ID(xch); DR(A); SM(DE, IMMU(1));
/** 0110 0001 1010 1100 xch %0, %e1 */