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Re: [PATCH] PR binutils/18257: Properly decode x86/Intel mask instructions.
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: Alexander Fomin <afomin dot mailbox at gmail dot com>
- Cc: Binutils <binutils at sourceware dot org>
- Date: Thu, 20 Aug 2015 04:59:47 -0700
- Subject: Re: [PATCH] PR binutils/18257: Properly decode x86/Intel mask instructions.
- Authentication-results: sourceware.org; auth=none
- References: <20150819161316 dot GA15909 at msticlxl57 dot ims dot intel dot com> <CAMe9rOqQg-TUF-UBos3zDGRDv=yVaEgxcpU6=RqCCOXRMyCF3A at mail dot gmail dot com> <20150820114228 dot GA46111 at msticlxl57 dot ims dot intel dot com>
On Thu, Aug 20, 2015 at 4:44 AM, Alexander Fomin
<afomin.mailbox@gmail.com> wrote:
> On Wed, Aug 19, 2015 at 09:16:55AM -0700, H.J. Lu wrote:
>> Please append the new testcases to i386/disassem.s, not
>> insert them in the beginning. OK with that change.
>>
>> Thanks.
>>
>> --
>> H.J.
>
> I've added nop padding and relocated all testcases.
> ChangeLog entries have also been updated.
Please fix ChangeLog entries.
> Alexander
> ---
> opcodes/
>
> PR binutils/18257
> * i386-dis.c Use MOD_TABLE for most of mask instructions.
^ Missing `:' .
> (MOD enum) Add MOD_VEX_W_0_0F41_P_0_LEN_1,
MOD_VEX_W_1_0F41_P_0_LEN_1,
^ Missing `:' .
> MOD_VEX_W_0_0F41_P_2_LEN_1, MOD_VEX_W_1_0F41_P_2_LEN_1,
> MOD_VEX_W_0_0F42_P_0_LEN_1, MOD_VEX_W_1_0F42_P_0_LEN_1,
> MOD_VEX_W_0_0F42_P_2_LEN_1, MOD_VEX_W_1_0F42_P_2_LEN_1,
> MOD_VEX_W_0_0F44_P_0_LEN_1, MOD_VEX_W_1_0F44_P_0_LEN_1,
> MOD_VEX_W_0_0F44_P_2_LEN_1, MOD_VEX_W_1_0F44_P_2_LEN_1,
> MOD_VEX_W_0_0F45_P_0_LEN_1, MOD_VEX_W_1_0F45_P_0_LEN_1,
> MOD_VEX_W_0_0F45_P_2_LEN_1, MOD_VEX_W_1_0F45_P_2_LEN_1,
> MOD_VEX_W_0_0F46_P_0_LEN_1, MOD_VEX_W_1_0F46_P_0_LEN_1,
> MOD_VEX_W_0_0F46_P_2_LEN_1, MOD_VEX_W_1_0F46_P_2_LEN_1,
> MOD_VEX_W_0_0F47_P_0_LEN_1, MOD_VEX_W_1_0F47_P_0_LEN_1,
> MOD_VEX_W_0_0F47_P_2_LEN_1, MOD_VEX_W_1_0F47_P_2_LEN_1,
> MOD_VEX_W_0_0F4A_P_0_LEN_1, MOD_VEX_W_1_0F4A_P_0_LEN_1,
> MOD_VEX_W_0_0F4A_P_2_LEN_1, MOD_VEX_W_1_0F4A_P_2_LEN_1,
> MOD_VEX_W_0_0F4B_P_0_LEN_1, MOD_VEX_W_1_0F4B_P_0_LEN_1,
> MOD_VEX_W_0_0F4B_P_2_LEN_1, MOD_VEX_W_0_0F91_P_0_LEN_0,
> MOD_VEX_W_1_0F91_P_0_LEN_0, MOD_VEX_W_0_0F91_P_2_LEN_0,
> MOD_VEX_W_1_0F91_P_2_LEN_0, MOD_VEX_W_0_0F92_P_0_LEN_0,
> MOD_VEX_W_0_0F92_P_2_LEN_0, MOD_VEX_W_0_0F92_P_3_LEN_0,
> MOD_VEX_W_1_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
> MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_W_0_0F93_P_3_LEN_0,
> MOD_VEX_W_1_0F93_P_3_LEN_0, MOD_VEX_W_0_0F98_P_0_LEN_0,
> MOD_VEX_W_1_0F98_P_0_LEN_0, MOD_VEX_W_0_0F98_P_2_LEN_0,
> MOD_VEX_W_1_0F98_P_2_LEN_0, MOD_VEX_W_0_0F99_P_0_LEN_0,
> MOD_VEX_W_1_0F99_P_0_LEN_0, MOD_VEX_W_0_0F99_P_2_LEN_0,
> MOD_VEX_W_1_0F99_P_2_LEN_0, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
> MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
> MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
> MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
> MOD_VEX_W_1_0F3A33_P_2_LEN_0.
> (vex_w_table) Replace terminals with MOD_TABLE entries for
^ Missing `:' .
> most of mask instructions.
>
> gas/testsuite
>
> PR binutils/18257
> * gas/i386/disassem.s Add mask instructions with invalid ModR/M byte.
^ Missing `:' .
> Add nop padding for existing instructions.
> * gas/i386/x86-64-disassem.s Likewise
^ Missing `:' .
> * gas/i386/disassem.d Add mask instructions with invalid ModR/M byte disassembly.
> Update disassembly for existing instructions to reflect nop padding.
Just use
* gas/i386/disassem.d: Updated.
> * gas/i386/x86-64-disassem.d Likewise.
>
>
OK with the fixed ChangeLog entries.
Thanks.
--
H.J.