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[PATCH 2/3] [aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insn
- From: Yao Qi <qiyaoltc at gmail dot com>
- To: marcus dot shawcroft at gmail dot com
- Cc: gdb-patches at sourceware dot org, binutils at sourceware dot org
- Date: Fri, 2 Oct 2015 12:23:58 +0100
- Subject: [PATCH 2/3] [aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insn
- Authentication-results: sourceware.org; auth=none
- References: <CAFqB+Px8-V8eojj8T66_zrM6krPeGXBVLU9h+_j5yEcrk0MMJg at mail dot gmail dot com> <1443785039-24602-1-git-send-email-yao dot qi at linaro dot org>
We want to use disas_aarch64_insn inside GDB to decode instructions, so
this patch exposes it and rename it to aarch64_decode_insn to follow
the conventions of other interfaces. This patch also change argument
insn type from uint32_t to aarch64_insn.
include/opcode:
2015-10-02 Yao Qi <yao.qi@linaro.org>
* aarch64.h (aarch64_decode_insn): Declare it.
opcodes:
2015-10-02 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c (disas_aarch64_insn): Remove static. Change
argument insn type to aarch64_insn. Rename to ...
(aarch64_decode_insn): ... it.
(print_insn_aarch64_word): Caller updated.
---
include/opcode/aarch64.h | 3 +++
opcodes/aarch64-dis.c | 9 +++++----
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index dcf0fef..d0c7489 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -925,6 +925,9 @@ aarch64_stack_pointer_p (const aarch64_opnd_info *);
extern
int aarch64_zero_register_p (const aarch64_opnd_info *);
+extern
+int aarch64_decode_insn (aarch64_insn, aarch64_inst *);
+
/* Given an operand qualifier, return the expected data element size
of a qualified operand. */
extern unsigned char
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index e0faeb5..fe3caac 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2029,10 +2029,11 @@ user_friendly_fixup (aarch64_inst *inst)
}
}
-/* Decode INSN and fill in *INST the instruction information. */
+/* Decode INSN and fill in *INST the instruction information. Return zero
+ on success. */
-static int
-disas_aarch64_insn (uint32_t insn, aarch64_inst *inst)
+int
+aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst)
{
const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
@@ -2171,7 +2172,7 @@ print_insn_aarch64_word (bfd_vma pc,
addresses, since the addend is not currently pc-relative. */
pc = 0;
- ret = disas_aarch64_insn (word, &inst);
+ ret = aarch64_decode_insn (word, &inst);
if (((word >> 21) & 0x3ff) == 1)
{
--
1.9.1