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[AArch64][Patch 5/5] Add instruction PSB CSYNC
- From: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- To: binutils at sourceware dot org
- Date: Wed, 9 Dec 2015 11:14:57 +0000
- Subject: [AArch64][Patch 5/5] Add instruction PSB CSYNC
- Authentication-results: sourceware.org; auth=none
- References: <56680B00 dot 6000705 at foss dot arm dot com>
Hello,
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds the instruction to
binutils as a HINT alias that takes an operand.
A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the
operand to PSB. A parser for the operand type is added to the assembler
and a printer to the disassembler. The operand name "csync" is added to
the list of HINT options with HINT number #17. Encoding and decoding of
the operand is handled by the ins_hint/ext_hint functions added in the
preceding patches.
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
Ok for trunk?
Matthew
gas/
2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
(parse_barrier_psb): New.
(parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
(md_begin): Set up aarch64_hint_opt_hsh.
gas/testsuite/
2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/system-2.d: Enable the statistical profiling
extension. Update the expected output.
* gas/aarch64/system-2.s: Add tests for PSB CSYNC.
* gas/aarch64/system.d: Update the expected output.
include/opcode/
2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (aarch64_hint_options): Add "csync".
(aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
* aarch64-tbl.h (aarch64_feature_stat_profile): New.
(STAT_PROFILE): New.
(aarch64_opcode_table): Add "psb".
(AARCH64_OPERANDS): Add "BARRIER_PSB".
>From 32bb80ea13276f830a05f4cfa56e3ef10b3b6236 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 12 Nov 2015 14:33:32 +0000
Subject: [PATCH 5/5] [AArch64][Patch 5/5] Add instruction PSB CSYNC
Change-Id: Id7d0fc3a557fe2660a1126136c144602d00512f1
---
gas/config/tc-aarch64.c | 56 +++++++++++++++++++++++++++++++++++-
gas/testsuite/gas/aarch64/system-2.d | 4 ++-
gas/testsuite/gas/aarch64/system-2.s | 4 +++
gas/testsuite/gas/aarch64/system.d | 2 +-
include/opcode/aarch64.h | 1 +
opcodes/aarch64-asm-2.c | 15 ++++++----
opcodes/aarch64-dis-2.c | 39 +++++++++++++------------
opcodes/aarch64-opc-2.c | 1 +
opcodes/aarch64-opc.c | 5 ++++
opcodes/aarch64-tbl.h | 9 +++++-
10 files changed, 108 insertions(+), 28 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index fb4dee1..16c3135 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -406,6 +406,7 @@ static struct hash_control *aarch64_reg_hsh;
static struct hash_control *aarch64_barrier_opt_hsh;
static struct hash_control *aarch64_nzcv_hsh;
static struct hash_control *aarch64_pldop_hsh;
+static struct hash_control *aarch64_hint_opt_hsh;
/* Stuff needed to resolve the label ambiguity
As:
@@ -3604,6 +3605,41 @@ parse_barrier (char **str)
return o->value;
}
+/* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
+ return 0 if successful. Otherwise return PARSE_FAIL. */
+
+static int
+parse_barrier_psb (char **str,
+ const struct aarch64_name_value_pair ** hint_opt)
+{
+ char *p, *q;
+ const struct aarch64_name_value_pair *o;
+
+ p = q = *str;
+ while (ISALPHA (*q))
+ q++;
+
+ o = hash_find_n (aarch64_hint_opt_hsh, p, q - p);
+ if (!o)
+ {
+ set_fatal_syntax_error
+ ( _("unknown or missing option to PSB"));
+ return PARSE_FAIL;
+ }
+
+ if (o->value != 0x11)
+ {
+ /* PSB only accepts option name 'CSYNC'. */
+ set_syntax_error
+ (_("the specified option is not accepted for PSB"));
+ return PARSE_FAIL;
+ }
+
+ *str = q;
+ *hint_opt = o;
+ return 0;
+}
+
/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
Returns the encoding for the option, or PARSE_FAIL.
@@ -5639,6 +5675,12 @@ sys_reg_ins:
inst.base.operands[i].prfop = aarch64_prfops + val;
break;
+ case AARCH64_OPND_BARRIER_PSB:
+ val = parse_barrier_psb (&str, &(info->hint_option));
+ if (val == PARSE_FAIL)
+ goto failure;
+ break;
+
default:
as_fatal (_("unhandled operand code %d"), operands[i]);
}
@@ -7502,7 +7544,8 @@ md_begin (void)
|| (aarch64_reg_hsh = hash_new ()) == NULL
|| (aarch64_barrier_opt_hsh = hash_new ()) == NULL
|| (aarch64_nzcv_hsh = hash_new ()) == NULL
- || (aarch64_pldop_hsh = hash_new ()) == NULL)
+ || (aarch64_pldop_hsh = hash_new ()) == NULL
+ || (aarch64_hint_opt_hsh = hash_new ()) == NULL)
as_fatal (_("virtual memory exhausted"));
fill_instruction_hash_table ();
@@ -7598,6 +7641,17 @@ md_begin (void)
(void *) (aarch64_prfops + i));
}
+ for (i = 0; aarch64_hint_options[i].name != NULL; i++)
+ {
+ const char* name = aarch64_hint_options[i].name;
+
+ checked_hash_insert (aarch64_hint_opt_hsh, name,
+ (void *) (aarch64_hint_options + i));
+ /* Also hash the name in the upper case. */
+ checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
+ (void *) (aarch64_hint_options + i));
+ }
+
/* Set the cpu variant based on the command-line options. */
if (!mcpu_cpu_opt)
mcpu_cpu_opt = march_cpu_opt;
diff --git a/gas/testsuite/gas/aarch64/system-2.d b/gas/testsuite/gas/aarch64/system-2.d
index 9b379cf..f999348 100644
--- a/gas/testsuite/gas/aarch64/system-2.d
+++ b/gas/testsuite/gas/aarch64/system-2.d
@@ -1,4 +1,4 @@
-#as: -march=armv8.2-a
+#as: -march=armv8.2-a+profile
#objdump: -dr
.*: file format .*
@@ -8,3 +8,5 @@ Disassembly of section \.text:
0000000000000000 <.*>:
0: d503221f esb
4: d503221f esb
+ 8: d503223f psb csync
+ c: d503223f psb csync
diff --git a/gas/testsuite/gas/aarch64/system-2.s b/gas/testsuite/gas/aarch64/system-2.s
index 9b7f216..3402e76 100644
--- a/gas/testsuite/gas/aarch64/system-2.s
+++ b/gas/testsuite/gas/aarch64/system-2.s
@@ -4,3 +4,7 @@
/* RAS Extension. */
esb
hint #0x10
+
+ /* Statistical profiling. */
+ psb csync
+ hint #0x11
diff --git a/gas/testsuite/gas/aarch64/system.d b/gas/testsuite/gas/aarch64/system.d
index d4dcf86..2da13ee 100644
--- a/gas/testsuite/gas/aarch64/system.d
+++ b/gas/testsuite/gas/aarch64/system.d
@@ -29,7 +29,7 @@ Disassembly of section \.text:
54: d50321df hint #0xe
58: d50321ff hint #0xf
5c: d503221f (hint #0x10|esb)
- 60: d503223f hint #0x11
+ 60: d503223f (hint #0x11|psb csync)
64: d503225f hint #0x12
68: d503227f hint #0x13
6c: d503229f hint #0x14
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index c85baca..3513574 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -234,6 +234,7 @@ enum aarch64_opnd
AARCH64_OPND_BARRIER, /* Barrier operand. */
AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
AARCH64_OPND_PRFOP, /* Prefetch operation. */
+ AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
};
/* Qualifier constrains an operand. It either specifies a variant of an
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 6bb0806..02eeb92 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -344,6 +344,7 @@ const struct aarch64_name_value_pair aarch64_barrier_options[16] =
const struct aarch64_name_value_pair aarch64_hint_options[] =
{
+ { "csync", 0x11 }, /* PSB CSYNC. */
{ NULL, 0x0 },
};
@@ -2729,6 +2730,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "#0x%02x", opnd->prfop->value);
break;
+ case AARCH64_OPND_BARRIER_PSB:
+ snprintf (buf, size, "%s", opnd->hint_option->name);
+ break;
+
default:
assert (0);
}
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 9e743db..35f950f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1303,6 +1303,8 @@ static const aarch64_feature_set aarch64_feature_v8_2 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
static const aarch64_feature_set aarch64_feature_fp_f16 =
AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
+static const aarch64_feature_set aarch64_feature_stat_profile =
+ AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -1314,6 +1316,7 @@ static const aarch64_feature_set aarch64_feature_fp_f16 =
#define RDMA &aarch64_feature_rdma
#define FP_F16 &aarch64_feature_fp_f16
#define RAS &aarch64_feature_ras
+#define STAT_PROFILE &aarch64_feature_stat_profile
#define ARMV8_2 &aarch64_feature_v8_2
struct aarch64_opcode aarch64_opcode_table[] =
@@ -2460,6 +2463,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"sev", 0xd503209f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
{"sevl", 0xd50320bf, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
{"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS},
+ {"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE,
+ OP1 (BARRIER_PSB), {}, F_ALIAS },
{"clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, CORE, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)},
{"dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
{"dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
@@ -2662,4 +2667,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \
"the ISB option name SY or an optional 4-bit unsigned immediate") \
Y(SYSTEM, prfop, "PRFOP", 0, F(), \
- "a prefetch operation specifier")
+ "a prefetch operation specifier") \
+ Y (SYSTEM, hint, "BARRIER_PSB", 0, F (), \
+ "the PSB option name CSYNC")
--
2.1.4