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[PATCH, committed] Implement Intel OSPKE instructions
- From: "H.J. Lu" <hongjiu dot lu at intel dot com>
- To: binutils at sourceware dot org
- Date: Wed, 9 Dec 2015 08:06:59 -0800
- Subject: [PATCH, committed] Implement Intel OSPKE instructions
- Authentication-results: sourceware.org; auth=none
- Reply-to: "H.J. Lu" <hjl dot tools at gmail dot com>
This patch implements Intel OSPKE instructions documented in Intel64
and IA-32 Architectures Software Developerâs Manual Volume 2, September
2015.
Checked into master. I am backporting it to 2.26.
H.J.
---
gas/testsuite/
* gas/i386/i386.exp: Run ospke and x86-64-ospke.
* gas/i386/ospke.d: New file.
* gas/i386/ospke.s: Likewise.
* gas/i386/x86-64-ospke.d: Likewise.
opcodes/
* i386-dis.c (MOD_0F01_REG_5): New.
(RM_0F01_REG_5): Likewise.
(reg_table): Use MOD_0F01_REG_5.
(mod_table): Add MOD_0F01_REG_5.
(rm_table): Add RM_0F01_REG_5.
* i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
(cpu_flags): Add CpuOSPKE.
* i386-opc.h (CpuOSPKE): New.
(i386_cpu_flags): Add cpuospke.
* i386-opc.tbl: Add rdpkru and wrpkru instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
---
gas/config/tc-i386.c | 2 +
gas/testsuite/ChangeLog | 7 +
gas/testsuite/gas/i386/i386.exp | 2 +
gas/testsuite/gas/i386/ospke.d | 12 +
gas/testsuite/gas/i386/ospke.s | 6 +
gas/testsuite/gas/i386/x86-64-ospke.d | 13 +
opcodes/ChangeLog | 15 +
opcodes/i386-dis.c | 20 +-
opcodes/i386-gen.c | 3 +
opcodes/i386-init.h | 221 +-
opcodes/i386-opc.h | 3 +
opcodes/i386-opc.tbl | 7 +
opcodes/i386-tbl.h | 10420 ++++++++++++++++----------------
13 files changed, 5426 insertions(+), 5305 deletions(-)
create mode 100644 gas/testsuite/gas/i386/ospke.d
create mode 100644 gas/testsuite/gas/i386/ospke.s
create mode 100644 gas/testsuite/gas/i386/x86-64-ospke.d
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index d341193..1573043 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -950,6 +950,8 @@ static const arch_entry cpu_arch[] =
CPU_CLZERO_FLAGS, 0, 0 },
{ STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
CPU_MWAITX_FLAGS, 0, 0 },
+ { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
+ CPU_OSPKE_FLAGS, 0, 0 },
};
#ifdef I386COFF
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 5978a3f..d0f5dea 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run ospke and x86-64-ospke.
+ * gas/i386/ospke.d: New file.
+ * gas/i386/ospke.s: Likewise.
+ * gas/i386/x86-64-ospke.d: Likewise.
+
2015-12-09 Jan Beulich <jbeulich@suse.com>
* gas/elf/file.d: Allow arbitrary entries at the beginning of
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 1739ba9..d881cd8 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -343,6 +343,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "disassem"
run_dump_test "mwaitx-bdver4"
run_list_test "mwaitx-reg"
+ run_dump_test "ospke"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
@@ -729,6 +730,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
+ run_dump_test "x86-64-ospke"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
diff --git a/gas/testsuite/gas/i386/ospke.d b/gas/testsuite/gas/i386/ospke.d
new file mode 100644
index 0000000..6e0afb0
--- /dev/null
+++ b/gas/testsuite/gas/i386/ospke.d
@@ -0,0 +1,12 @@
+#name: i386 OSPKE insns
+#objdump: -dw
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 01 ee rdpkru
+[ ]*[a-f0-9]+: 0f 01 ef wrpkru
+#pass
diff --git a/gas/testsuite/gas/i386/ospke.s b/gas/testsuite/gas/i386/ospke.s
new file mode 100644
index 0000000..76b66e7
--- /dev/null
+++ b/gas/testsuite/gas/i386/ospke.s
@@ -0,0 +1,6 @@
+# Check OSPKE instructions.
+
+ .text
+_start:
+ rdpkru
+ wrpkru
diff --git a/gas/testsuite/gas/i386/x86-64-ospke.d b/gas/testsuite/gas/i386/x86-64-ospke.d
new file mode 100644
index 0000000..88e7ec0
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-ospke.d
@@ -0,0 +1,13 @@
+#source: ospke.s
+#name: x86-64 OSPKE insns
+#objdump: -dw
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 01 ee rdpkru
+[ ]*[a-f0-9]+: 0f 01 ef wrpkru
+#pass
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 221f8f7..255a8c6 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,18 @@
+2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (MOD_0F01_REG_5): New.
+ (RM_0F01_REG_5): Likewise.
+ (reg_table): Use MOD_0F01_REG_5.
+ (mod_table): Add MOD_0F01_REG_5.
+ (rm_table): Add RM_0F01_REG_5.
+ * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
+ (cpu_flags): Add CpuOSPKE.
+ * i386-opc.h (CpuOSPKE): New.
+ (i386_cpu_flags): Add cpuospke.
+ * i386-opc.tbl: Add rdpkru and wrpkru instructions.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
2015-12-07 DJ Delorie <dj@redhat.com>
* rl78-decode.opc: Enable MULU for all ISAs.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index ae18cf2..1b4c51a 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -758,6 +758,7 @@ enum
MOD_0F01_REG_1,
MOD_0F01_REG_2,
MOD_0F01_REG_3,
+ MOD_0F01_REG_5,
MOD_0F01_REG_7,
MOD_0F12_PREFIX_0,
MOD_0F13,
@@ -929,6 +930,7 @@ enum
RM_0F01_REG_1,
RM_0F01_REG_2,
RM_0F01_REG_3,
+ RM_0F01_REG_5,
RM_0F01_REG_7,
RM_0FAE_REG_5,
RM_0FAE_REG_6,
@@ -3554,7 +3556,7 @@ static const struct dis386 reg_table[][8] = {
{ MOD_TABLE (MOD_0F01_REG_2) },
{ MOD_TABLE (MOD_0F01_REG_3) },
{ "smswD", { Sv }, 0 },
- { Bad_Opcode },
+ { MOD_TABLE (MOD_0F01_REG_5) },
{ "lmsw", { Ew }, 0 },
{ MOD_TABLE (MOD_0F01_REG_7) },
},
@@ -11685,6 +11687,11 @@ static const struct dis386 mod_table[][2] = {
{ RM_TABLE (RM_0F01_REG_3) },
},
{
+ /* MOD_0F01_REG_5 */
+ { Bad_Opcode },
+ { RM_TABLE (RM_0F01_REG_5) },
+ },
+ {
/* MOD_0F01_REG_7 */
{ "invlpg", { Mb }, 0 },
{ RM_TABLE (RM_0F01_REG_7) },
@@ -12429,6 +12436,17 @@ static const struct dis386 rm_table[][8] = {
{ "invlpga", { Skip_MODRM }, 0 },
},
{
+ /* RM_0F01_REG_5 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "rdpkru", { Skip_MODRM }, 0 },
+ { "wrpkru", { Skip_MODRM }, 0 },
+ },
+ {
/* RM_0F01_REG_7 */
{ "swapgs", { Skip_MODRM }, 0 },
{ "rdtscp", { Skip_MODRM }, 0 },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 18115df..071355b 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -255,6 +255,8 @@ static initializer cpu_flag_init[] =
"CpuCLZERO" },
{ "CPU_MWAITX_FLAGS",
"CpuMWAITX" },
+ { "CPU_OSPKE_FLAGS",
+ "CpuOSPKE" },
};
static initializer operand_type_init[] =
@@ -461,6 +463,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuAVX512VBMI),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
+ BITFIELD (CpuOSPKE),
BITFIELD (CpuAMD64),
BITFIELD (CpuIntel64),
#ifdef CpuUnused
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 0dbf296..6a77dab 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -198,6 +198,8 @@ enum
CpuMWAITX,
/* Clzero instruction required */
CpuCLZERO,
+ /* OSPKE instruction required */
+ CpuOSPKE,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
@@ -308,6 +310,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx512vbmi:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
+ unsigned int cpuospke:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
unsigned int cpuamd64:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index ed6fe63..cb518ae 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -5951,3 +5951,10 @@ mwaitx, 3, 0xf01, 0xfb, 2, CpuMWAITX|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No
// Need to ensure only "mwaitx %rax,%rcx,%rbx" is accepted.
mwaitx, 3, 0xf01, 0xfb, 2, CpuMWAITX|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|NoRex64|NoAVX, { Reg64, Reg64, Reg64 }
// MONITORX/MWAITX instructions end
+
+// OSPKE instructions.
+
+rdpkru, 0, 0xf01ee, None, 3, CpuOSPKE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+wrpkru, 0, 0xf01ef, None, 3, CpuOSPKE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+
+// OSPKE instructions end.