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[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.
- From: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- To: binutils at sourceware dot org
- Date: Fri, 11 Dec 2015 12:28:42 +0000
- Subject: [AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.
- Authentication-results: sourceware.org; auth=none
- References: <566AB800 dot 1090308 at foss dot arm dot com>
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Scalar Pairwise, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP
The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar
Pairwise instructions.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_XLANES_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
>From 317aa407fb0e8182fafe3790669a9ab8bcac6139 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Fri, 11 Sep 2015 17:55:18 +0100
Subject: [PATCH 12/14] [AArch64] Add FP16 Adv.SIMD Scalar Pairwise
instructions (IX).
---
gas/testsuite/gas/aarch64/advsimd-fp16.d | 20 +
gas/testsuite/gas/aarch64/advsimd-fp16.s | 16 +
opcodes/aarch64-asm-2.c | 604 ++++++------
opcodes/aarch64-dis-2.c | 1559 ++++++++++++++++--------------
opcodes/aarch64-opc-2.c | 86 +-
opcodes/aarch64-tbl.h | 16 +
6 files changed, 1204 insertions(+), 1097 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d
index 5abad7e..3b8506b 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.d
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d
@@ -499,3 +499,23 @@ Disassembly of section \.text:
[0-9a-f]+: 4f00fc01 fmov v1.8h, #2.000000000000000000e\+00
[0-9a-f]+: 0f03fe00 fmov v0.4h, #1.000000000000000000e\+00
[0-9a-f]+: 4f03fe00 fmov v0.8h, #1.000000000000000000e\+00
+ [0-9a-f]+: 7e70c841 fmaxnmp d1, v2.2d
+ [0-9a-f]+: 7e30c841 fmaxnmp s1, v2.2s
+ [0-9a-f]+: 5e30c841 fmaxnmp h1, v2.2h
+ [0-9a-f]+: 5e30c800 fmaxnmp h0, v0.2h
+ [0-9a-f]+: 7e70d841 faddp d1, v2.2d
+ [0-9a-f]+: 7e30d841 faddp s1, v2.2s
+ [0-9a-f]+: 5e30d841 faddp h1, v2.2h
+ [0-9a-f]+: 5e30d800 faddp h0, v0.2h
+ [0-9a-f]+: 7e70f841 fmaxp d1, v2.2d
+ [0-9a-f]+: 7e30f841 fmaxp s1, v2.2s
+ [0-9a-f]+: 5e30f841 fmaxp h1, v2.2h
+ [0-9a-f]+: 5e30f800 fmaxp h0, v0.2h
+ [0-9a-f]+: 7ef0c841 fminnmp d1, v2.2d
+ [0-9a-f]+: 7eb0c841 fminnmp s1, v2.2s
+ [0-9a-f]+: 5eb0c841 fminnmp h1, v2.2h
+ [0-9a-f]+: 5eb0c800 fminnmp h0, v0.2h
+ [0-9a-f]+: 7ef0f841 fminp d1, v2.2d
+ [0-9a-f]+: 7eb0f841 fminp s1, v2.2s
+ [0-9a-f]+: 5eb0f841 fminp h1, v2.2h
+ [0-9a-f]+: 5eb0f800 fminp h0, v0.2h
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s
index 75aacf6..c0ea786 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.s
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s
@@ -212,3 +212,19 @@
fmov v1.8h, #2.0
fmov v0.4h, #1.0
fmov v0.8h, #1.0
+
+ /* Adv.SIMD modified immediate. */
+
+ .macro scalar_pairwise, op
+ \op d1, v2.2d
+ \op s1, v2.2s
+ \op h1, v2.2h
+ \op h0, v0.2h
+ .endm
+
+ scalar_pairwise fmaxnmp
+ scalar_pairwise faddp
+ scalar_pairwise fmaxp
+ scalar_pairwise fminnmp
+ scalar_pairwise fminp
+
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index c359903..684df5d 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -484,6 +484,12 @@
QLF2(S_D, V_2D), \
}
+/* e.g. FMAXNMP <V><d>, <Vn>.<T>. */
+#define QL_SISD_PAIR_H \
+{ \
+ QLF2 (S_H, V_2H), \
+}
+
/* e.g. ADDP <V><d>, <Vn>.<T>. */
#define QL_SISD_PAIR_D \
{ \
@@ -2002,10 +2008,20 @@ struct aarch64_opcode aarch64_opcode_table[] =
/* AdvSIMD scalar pairwise. */
{"addp", 0x5e31b800, 0xff3ffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR_D, F_SIZEQ},
{"fmaxnmp", 0x7e30c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
+ {"fmaxnmp", 0x5e30c800, 0xfffffc00, asisdpair, 0, SIMD_F16,
+ OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ},
{"faddp", 0x7e30d800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
+ {"faddp", 0x5e30d800, 0xfffffc00, asisdpair, 0, SIMD_F16,
+ OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ},
{"fmaxp", 0x7e30f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
+ {"fmaxp", 0x5e30f800, 0xfffffc00, asisdpair, 0, SIMD_F16,
+ OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ},
{"fminnmp", 0x7eb0c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
+ {"fminnmp", 0x5eb0c800, 0xfffffc00, asisdpair, 0, SIMD_F16,
+ OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ},
{"fminp", 0x7eb0f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
+ {"fminp", 0x5eb0f800, 0xfffffc00, asisdpair, 0, SIMD_F16,
+ OP2 (Sd, Vn), QL_SISD_PAIR_H, F_SIZEQ},
/* AdvSIMD scalar three same. */
{"sqadd", 0x5e200c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
{"sqsub", 0x5e202c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
--
2.1.4