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[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.
- From: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- To: binutils at sourceware dot org
- Date: Fri, 11 Dec 2015 12:35:11 +0000
- Subject: [AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.
- Authentication-results: sourceware.org; auth=none
- References: <566AB800 dot 1090308 at foss dot arm dot com>
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Scalar Shift By Immediate to support
FP16, making this support available when +simd+fp16 is enabled.
The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.
The general form for these instructions is
<OP> <Hd>, <Hs>, #<imm>
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
Ok for trunk?
Matthew
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
by immediate instructions.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD scalar shift by immediate group.
>From 944ede10a9fccbb0babda36abdc689cec30e49a4 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 10 Sep 2015 18:04:55 +0100
Subject: [PATCH 14/14] [AArch64] Add FP16 Adv.SIMD scalar shift by immediate
instructions (XI).
---
gas/testsuite/gas/aarch64/advsimd-fp16.d | 16 +
gas/testsuite/gas/aarch64/advsimd-fp16.s | 14 +
opcodes/aarch64-asm-2.c | 604 ++++++-------
opcodes/aarch64-dis-2.c | 1352 +++++++++++++++---------------
opcodes/aarch64-opc-2.c | 86 +-
opcodes/aarch64-tbl.h | 14 +
6 files changed, 1069 insertions(+), 1017 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d
index a6792ee..b29c9da 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.d
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d
@@ -547,3 +547,19 @@ Disassembly of section \.text:
[0-9a-f]+: 6f1dfc41 fcvtzu v1.8h, v2.8h, #3
[0-9a-f]+: 2f1ffc00 fcvtzu v0.4h, v0.4h, #1
[0-9a-f]+: 6f1ffc00 fcvtzu v0.8h, v0.8h, #1
+ [0-9a-f]+: 5f7de441 scvtf d1, d2, #3
+ [0-9a-f]+: 5f3de441 scvtf s1, s2, #3
+ [0-9a-f]+: 5f1de441 scvtf h1, h2, #3
+ [0-9a-f]+: 5f1fe400 scvtf h0, h0, #1
+ [0-9a-f]+: 5f7dfc41 fcvtzs d1, d2, #3
+ [0-9a-f]+: 5f3dfc41 fcvtzs s1, s2, #3
+ [0-9a-f]+: 5f1dfc41 fcvtzs h1, h2, #3
+ [0-9a-f]+: 5f1ffc00 fcvtzs h0, h0, #1
+ [0-9a-f]+: 7f7de441 ucvtf d1, d2, #3
+ [0-9a-f]+: 7f3de441 ucvtf s1, s2, #3
+ [0-9a-f]+: 7f1de441 ucvtf h1, h2, #3
+ [0-9a-f]+: 7f1fe400 ucvtf h0, h0, #1
+ [0-9a-f]+: 7f7dfc41 fcvtzu d1, d2, #3
+ [0-9a-f]+: 7f3dfc41 fcvtzu s1, s2, #3
+ [0-9a-f]+: 7f1dfc41 fcvtzu h1, h2, #3
+ [0-9a-f]+: 7f1ffc00 fcvtzu h0, h0, #1
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s
index 1eb7418..8be4854 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.s
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s
@@ -244,3 +244,17 @@
shift_imm fcvtzs
shift_imm ucvtf
shift_imm fcvtzu
+
+ /* Adv.SIMD scalar shift by immediate. */
+
+ .macro sshift_imm, op
+ \op d1, d2, #3
+ \op s1, s2, #3
+ \op h1, h2, #3
+ \op h0, h0, #1
+ .endm
+
+ sshift_imm scvtf
+ sshift_imm fcvtzs
+ sshift_imm ucvtf
+ sshift_imm fcvtzu
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 20dd175..7138c70 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -375,6 +375,12 @@
QLF3(S_D , S_D , S_D ) \
}
+/* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
+#define QL_SSHIFT_H \
+{ \
+ QLF3 (S_H, S_H, S_H) \
+}
+
/* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */
#define QL_SSHIFTN \
{ \
@@ -2100,7 +2106,11 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"sqshrn", 0x5f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
{"sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
{"scvtf", 0x5f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
+ {"scvtf", 0x5f10e400, 0xff80fc00, asisdshf, 0, SIMD_F16,
+ OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
{"fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
+ {"fcvtzs", 0x5f10fc00, 0xff80fc00, asisdshf, 0, SIMD_F16,
+ OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
{"ushr", 0x7f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
{"usra", 0x7f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
{"urshr", 0x7f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
@@ -2114,7 +2124,11 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"uqshrn", 0x7f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
{"uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
{"ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
+ {"ucvtf", 0x7f10e400, 0xff80fc00, asisdshf, 0, SIMD_F16,
+ OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
{"fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
+ {"fcvtzu", 0x7f10fc00, 0xff80fc00, asisdshf, 0, SIMD_F16,
+ OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_H, 0},
/* Bitfield. */
{"sbfm", 0x13000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
{"sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
--
2.1.4