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[PATCH][RX] v1 disassembly fix
- From: Yoshinori Sato <ysato at users dot sourceforge dot jp>
- To: binutils at sourceware dot org
- Cc: Yoshinori Sato <ysato at users dot sourceforge dot jp>
- Date: Tue, 22 Dec 2015 02:37:12 +0900
- Subject: [PATCH][RX] v1 disassembly fix
- Authentication-results: sourceware.org; auth=none
- References: <1450719432-16791-1-git-send-email-ysato at users dot sourceforge dot jp>
include/opcode/ChangeLog
* rx.h (rx_decode_opcode_isa): New. Add isa flag.
opcodes/ChangeLog
* rx-decode.opc (rx_decode_opcode_isa): Rename from rx_decode_opcode
(mulhi): Add v1 mode.
(mullo): Likewise.
(machi): Likewise.
(maclo): Likewise.
(mvtachi): Likewise.
(mvtaclo): Likewise.
(mvfachi): Likewise.
(mvfacmi): Likewise.
(mvfaclo): Likewise.
(racw): Likewise.
(mvtacgu): Operamd order fix.
(rx_decode_opcode): New. compatibility function.
* rx-dis.c (print_insn_rx): Use rx_decode_opcode_isa.
---
include/opcode/rx.h | 1 +
opcodes/rx-decode.opc | 160 ++++++++++++++++++++++++++++++++++++++++++--------
opcodes/rx-dis.c | 3 +-
3 files changed, 138 insertions(+), 26 deletions(-)
diff --git a/include/opcode/rx.h b/include/opcode/rx.h
index eda0ee3..0673944 100644
--- a/include/opcode/rx.h
+++ b/include/opcode/rx.h
@@ -242,6 +242,7 @@ typedef struct
registers. 32..47 are condition codes. */
int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *);
+int rx_decode_opcode_isa (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *, int);
#ifdef __cplusplus
}
diff --git a/opcodes/rx-decode.opc b/opcodes/rx-decode.opc
index f95ff45..a670bee 100644
--- a/opcodes/rx-decode.opc
+++ b/opcodes/rx-decode.opc
@@ -260,10 +260,11 @@ rx_disp (int n, int type, int reg, int size, LocalData * ld)
#define F_OSZC rx->flags_0 = rx->flags_s = xO|xS|xZ|xC;
int
-rx_decode_opcode (unsigned long pc AU,
- RX_Opcode_Decoded * rx,
- int (* getbyte)(void *),
- void * ptr)
+rx_decode_opcode_isa (unsigned long pc AU,
+ RX_Opcode_Decoded * rx,
+ int (* getbyte)(void *),
+ void * ptr,
+ int isa)
{
LocalData lds, * ld = &lds;
unsigned char op[20] = {0};
@@ -844,35 +845,135 @@ rx_decode_opcode (unsigned long pc AU,
/*----------------------------------------------------------------------*/
/* HI/LO stuff */
-/** 1111 1101 0000 a000 srca srcb mulhi %1, %2, %0 */
- ID(mulhi); DR(a+32); SR(srca); S2R(srcb); F_____;
+/** 1111 1101 0000 a000 srca srcb */
+ switch (isa)
+ {
+ case 1:
+ SYNTAX("mulhi %1, %2");
+ ID(mulhi); SR(srca); S2R(srcb); F_____;
+ break;
+ case 2:
+ SYNTAX("mulhi %1, %2, %0");
+ ID(mulhi); DR(a+32); SR(srca); S2R(srcb); F_____;
+ break;
+ }
-/** 1111 1101 0000 a001 srca srcb mullo %1, %2, %0 */
- ID(mullo); DR(a+32); SR(srca); S2R(srcb); F_____;
+/** 1111 1101 0000 a001 srca srcb */
+ switch (isa)
+ {
+ case 1:
+ SYNTAX("mullo %1, %2");
+ ID(mullo); SR(srca); S2R(srcb); F_____;
+ break;
+ case 2:
+ SYNTAX("mullo %1, %2, %0");
+ ID(mullo); DR(a+32); SR(srca); S2R(srcb); F_____;
+ break;
+ }
-/** 1111 1101 0000 a100 srca srcb machi %1, %2, %0 */
- ID(machi); DR(a+32); SR(srca); S2R(srcb); F_____;
+/** 1111 1101 0000 a100 srca srcb */
+ switch (isa)
+ {
+ case 1:
+ SYNTAX("machi %1, %2");
+ ID(machi); SR(srca); S2R(srcb); F_____;
+ break;
+ case 2:
+ SYNTAX("machi %1, %2, %0");
+ ID(machi); DR(a+32); SR(srca); S2R(srcb); F_____;
+ break;
+ }
-/** 1111 1101 0000 a101 srca srcb maclo %1, %2, %0 */
- ID(maclo); DR(a+32); SR(srca); S2R(srcb); F_____;
+/** 1111 1101 0000 a101 srca srcb */
+ switch (isa)
+ {
+ case 1:
+ SYNTAX("maclo %1, %2");
+ ID(maclo); SR(srca); S2R(srcb); F_____;
+ break;
+ case 2:
+ SYNTAX("maclo %1, %2, %0");
+ ID(maclo); DR(a+32); SR(srca); S2R(srcb); F_____;
+ break;
+ }
-/** 1111 1101 0001 0111 a000 rsrc mvtachi %1, %0 */
- ID(mvtachi); DR(a+32); SR(rsrc); F_____;
+/** 1111 1101 0001 0111 a000 rsrc */
+ switch (isa)
+ {
+ case 1:
+ SYNTAX("mvtachi %1");
+ ID(mvtachi); SR(rsrc); F_____;
+ break;
+ case 2:
+ SYNTAX("mvtachi %1, %0");
+ ID(mvtachi); DR(a+32); SR(rsrc); F_____;
+ break;
+ }
-/** 1111 1101 0001 0111 a001 rsrc mvtaclo %1, %0 */
- ID(mvtaclo); DR(a+32); SR(rsrc); F_____;
+/** 1111 1101 0001 0111 a001 rsrc */
+ switch (isa)
+ {
+ case 1:
+ SYNTAX("mvtaclo %1");
+ ID(mvtaclo); SR(rsrc); F_____;
+ break;
+ case 2:
+ SYNTAX("mvtaclo %1, %0");
+ ID(mvtaclo); DR(a+32); SR(rsrc); F_____;
+ break;
+ }
-/** 1111 1101 0001 111i a m00 rdst mvfachi #%2, %1, %0 */
- ID(mvfachi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
+/** 1111 1101 0001 111i a m00 rdst */
+ switch (isa)
+ {
+ case 1:
+ SYNTAX("mvfachi %0");
+ ID(mvfachi); DR(rdst); F_____;
+ break;
+ case 2:
+ SYNTAX("mvfachi #%2, %1, %0");
+ ID(mvfachi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
+ break;
+ }
-/** 1111 1101 0001 111i a m10 rdst mvfacmi #%2, %1, %0 */
- ID(mvfacmi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
+/** 1111 1101 0001 111i a m10 rdst */
+ switch (isa)
+ {
+ case 1:
+ SYNTAX("mvfacmi %0");
+ ID(mvfacmi); DR(rdst); F_____;
+ break;
+ case 2:
+ SYNTAX("mvfacmi #%2, %1, %0");
+ ID(mvfacmi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
+ break;
+ }
-/** 1111 1101 0001 111i a m01 rdst mvfaclo #%2, %1, %0 */
- ID(mvfaclo); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
+/** 1111 1101 0001 111i a m01 rdst */
+ switch (isa)
+ {
+ case 1:
+ SYNTAX("mvfaclo %0");
+ ID(mvfaclo); DR(rdst); F_____;
+ break;
+ case 2:
+ SYNTAX("mvfaclo #%2, %1, %0");
+ ID(mvfaclo); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
+ break;
+ }
-/** 1111 1101 0001 1000 a00i 0000 racw #%1, %0 */
- ID(racw); SC(i+1); DR(a+32); F_____;
+/** 1111 1101 0001 1000 a00i 0000 */
+ switch (isa)
+ {
+ case 1:
+ SYNTAX("racw %1");
+ ID(racw); SC(i+1); F_____;
+ break;
+ case 2:
+ SYNTAX("racw #%1, %0");
+ ID(racw); SC(i+1); DR(a+32); F_____;
+ break;
+ }
/*----------------------------------------------------------------------*/
/* SAT */
@@ -1081,7 +1182,7 @@ rx_decode_opcode (unsigned long pc AU,
/** 1111 1101 0001 111i a m11 rdst mvfacgu #%2, %1, %0 */
ID(mvfacgu); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
-/** 1111 1101 0001 0111 a011 rdst mvtacgu %0, %1 */
+/** 1111 1101 0001 0111 a011 rdst mvtacgu %1, %0 */
ID(mvtacgu); DR(a+32); SR(rdst); F_____;
/** 1111 1101 0001 1001 a00i 0000 racl #%1, %0 */
@@ -1118,3 +1219,12 @@ rx_decode_opcode (unsigned long pc AU,
return rx->n_bytes;
}
+
+int
+rx_decode_opcode (unsigned long pc AU,
+ RX_Opcode_Decoded * rx,
+ int (* getbyte)(void *),
+ void * ptr)
+{
+ return rx_decode_opcode_isa(pc, rx, getbyte, ptr, 2);
+}
diff --git a/opcodes/rx-dis.c b/opcodes/rx-dis.c
index 74ad726..c3abff6 100644
--- a/opcodes/rx-dis.c
+++ b/opcodes/rx-dis.c
@@ -96,7 +96,8 @@ print_insn_rx (bfd_vma addr, disassemble_info * dis)
rx_data.pc = addr;
rx_data.dis = dis;
- rv = rx_decode_opcode (addr, &opcode, rx_get_byte, &rx_data);
+ rv = rx_decode_opcode_isa (addr, &opcode, rx_get_byte, &rx_data,
+ dis->mach - bfd_mach_rx + 1);
dis->bytes_per_line = 10;
--
2.6.1