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Re: [12/16][binutils][AARCH64]Add relocation support for large memory model. [BFD]Create GOT section for TLSLE_MOVW_TPREL_G(1, 1_NC, 2).
[2.26] [PATCH] PR ld/19319: Regression: ld.bfd: 2.25.90.20151125 assertion fail ../../bfd/elf32-i386.c:5297
Re: [AArch64] Add feature flags and command line for ARMv8.2 FP16 support.
[AArch64] Add support for ARMv8.2 PSTATE.UAO.
[AArch64] Don't generate GOT entry for large model TLS LE relocation
[AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.
Re: [AArch64] Let aliased instructions be their preferred form.
[AArch64] Remove redundant calculation of plt stub destination for veneer
Re: [Aarch64] Support an ARMv8.2 system register.
[Aarch64] Support ARMv8.2 AT instructions
[AArch64][2.26] Backport ARMv8.2 command line option and feature flag
[AArch64][2.26] Backport ARMv8.2 FP16 AdvSIMD and Statistical Profiling support.
[AArch64][2.26] Backport support for ARMv8.1 Virtualization,Host Extensions.
[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.
Re: [AArch64][PATCH 1/2] Add ARMv8.2 instructions BFC and REV64.
[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
[AArch64][PATCH 1/2] Add support for RAS instruction ESB.
Re: [AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.
[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.
[AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.
[AArch64][PATCH 11/14] Add support for the 2H vector type.
[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.
[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.
[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
Re: [AArch64][PATCH 2/2] Add ARMv8.2 instruction alias REV64.
[AArch64][PATCH 2/2] Add RAS system registers.
[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
Re: [AArch64][PATCH 2/3] Adjust a utility function for floating point values.
[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
Re: [AArch64][PATCH 3/3] Add floating-point FP16 instructions
[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
[AArch64][Patch 4/5] Support HINT aliases taking operands.
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
[AArch64][Patch 5/5] Add instruction PSB CSYNC
[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.
[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.
[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.
[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.
[ARM] Enable CRC by default for ARMv8.1 and later.
[ARM] Support ARMv8.2 RAS extension.
[ARM][2.26] Backport ARMv8.2 architecture feature and command line option
[committed] correct nios2 _gp address computation
[committed] MAINTAINERS: Add myself as MIPS maintainer
Re: [GOLD] Add more params to relocate() and relocate_section()
Re: [GOLD] Edit PowerPC64 ELFv2 function entry code
Re: [GOLD] R_PPC64_ENTRY support
[GOLD] relocate() params
[PATCH 1/2] gas: don't get confused by .asci{i,z} after .struct
[PATCH 1/4] [RX] v2 instructions support
[PATCH 2/2] gas: consistently emit diagnostics for non-zero data emission to .bss/.struct
[PATCH 2/4] [RX] v2 instructions support
[PATCH 3/4] [RX] v2 instructions support
[PATCH 4/4] [RX] v2 instructions test case.
[Patch ARM ] Fix build attributes for armv8-a in case of assembler files that contain no directives
Re: [patch bfd] Mark sh5*-*-* and sh64*-*-* as obsolete
[patch bfd] Mark sh5*-*-* and sh64*-*-* as obsolete (Was: Re: New failures with .debug_ranges test)
[PATCH RFC] gas: don't process relocs for content-less sections
Re: [PATCH v2 1/4] gold: Take addend into account for calculating value of the local symbol for GOT.
[PATCH v2] ARM: Add support for thumb1 PCROP relocations.
[PATCH v3] ARM: Add support for thumb1 PCROP relocations.
[PATCH, ARM 1/7] Consolidate Thumb-1/Thumb-2 ISA detection
[PATCH, ARM 2/7] Add support for ARMv8-M Mainline without security extensions
[PATCH, ARM 3/7] Add assembler support for ARMv8-M Baseline without security extensions
[PATCH, ARM 4/7] Add support for linking ARMv8-M object files
[PATCH, ARM 6/7] Allow extension availability to depend on several architecture bits
[PATCH, ARM 7/7] Add support for ARMv8-M Mainline with DSP extension
[PATCH, ARM, 0/7] Add support for ARMv8-M
[PATCH, committed] Implement Intel OSPKE instructions
[PATCH, committed][2.26] Optimize R_386_GOT32/R_386_GOT32X only if addend is 0
Re: [PATCH] [GAS] sparc: support %dN and %qN syntax for FP registers.
[PATCH] [RFC] [GOLD] s390 -fsplit-stack support.
Re: [PATCH] [RFC] nios2: Fix initial PLT entry population
[PATCH] Add bfd_mach_rx_v2
[PATCH] arc/gas: Accept, but ignore, dummy arguments.
[PATCH] ARM: Add cantunwind when unwind info does not match start of section
[PATCH] ARM: Add support for SHF_ARM_NOREAD section flag
Re: [PATCH] ARM: Add support for thumb1 PCROP relocations.
[PATCH] ARM: Fix exidx coverage for relocatable builds
[PATCH] bfd: don't produce corrupt COFF symbol table due to long ELF file name symbols
[PATCH] Darwin: add and dump new header flags
[PATCH] ELF: don't re-order SHF_FILE symbols
[PATCH] Fix -flto on mingw (PR ld/18199)
[PATCH] gas/ELF: slightly relax elf/file*.d expectations
[PATCH] gas: free allocated symbol name in .cfi_label handling
Re: [PATCH] gold: Implement --long-plt flag.
[PATCH] gold: safe-ctype.h vs C++ system headers
[PATCH] ld: relax alignment requirements of compressed .debug_* section checks
[PATCH] nm: basic symbol type support for SysV-style symbol table dumping
[PATCH] opcodes/arc: Support dmb instruction with no operands
[PATCH] Optimize R_386_GOT32/R_386_GOT32X only if addend is 0
[PATCH] PR ld/19317: ld -r doesn't need plugin for slim lto object
[PATCH] PR ld/19319: Regression: ld.bfd: 2.25.90.20151125 assertion fail ../../bfd/elf32-i386.c:5297
[PATCH] Remove useless loop
[PATCH] rl78: Enable MULU for all ISAs.
[PATCH][ARC] Bug fixing and adding GAS tests.
RE: [PATCH][Binutils][ARM] ldah being disassembled as ldaexh
[PATCH][GAS][ARM] Autodetection tests
[PATCH][gold] PR ld/19317: ld -r doesn't need plugin for slim lto object
[PATCH][RX] instruction decoder various fix
[PATCH][RX] v1 disassembly fix
Re: [PING^2] [PATCH] PR gold/18609
[PUSHED/PATCH] arc/gas: Accept, but ignore, dummy arguments.
Re: [RFC PATCH 01/11] MIPS/BFD: Correct an FP ABI warning
Re: [RFC PATCH 02/11] MIPS/BFD: Use local pointers to target data in private data merge
Re: [RFC PATCH 03/11] MIPS/BFD: Suppress attribute checks for null input
Re: [RFC PATCH 04/11] MIPS/BFD: Fold the handling of input MIPS ABI flags together
Re: [RFC PATCH 05/11] MIPS/BFD: Factor out ELF file header flag checks
Re: [RFC PATCH 06/11] MIPS/BFD: Propagate the return status in attribute merging
Re: [RFC PATCH 07/11] MIPS/BFD: Move attribute check after ELF file header flag check
Re: [RFC PATCH 08/11] MIPS/BFD: Factor out ABI flag merging
Re: [RFC PATCH 09/11] MIPS/LD: Convert ELF linker emulation option macros to an enum
Re: [RFC PATCH 10/11] BFD: Pass link information to `bfd_merge_private_bfd_data'
[RFC PATCH, ARM 5/7] Add support for ARMv8-M security extensions instructions
[RFC PATCH, binutils, ARM 1/9] Refactor Cortex-A8 erratum workaround in preparation
[RFC PATCH, binutils, ARM 2/9] Factor our stub creation in ARM backend
[RFC PATCH, binutils, ARM 3/9] Allow stubs without associated input section in ARM backend
[RFC PATCH, binutils, ARM 4/9] Use getters/setters to access ARM branch type
[RFC PATCH, binutils, ARM 5/9] Allow veneers to claim veneered symbols
[RFC PATCH, binutils, ARM 6/9] Add support for ARMv8-M Secure Gateway veneer generation
[RFC PATCH, binutils, ARM 7/9] Add support for creating import libraries
[RFC PATCH, binutils, ARM 8/9] Add support for creating ARM v8-M secure extensions import libraries
[RFC PATCH, binutils, ARM 9/9] Add support for stable secure gateway veneers addresses
Re: [RFC] Add IFUNC support for MIPS (v3)
[rx] Fix p_vaddr reconstruction logic.
addr2line vs. inlined C functions called from C++
Re: ARC port broken reloc processing
binutils/configure update
Bootstrap failure because of warning in tc-i386.c
Commit: Fix formatting in coff-i386.c
Commit: MSP430: Remove redundant silicon errata
Commit: RX: Fix relaxation problems when linking with --no-keep-memory
Re: differences in generated ldscripts for native and cross builds
Don't use BFD_TRADITIONAL_FORMAT flag in COFF support
Enable 2 operand form of powerpc mfcr with -many
FAIL: Link with zlib-gabi compressed debug output
Fix powerpc64 segfault caused by zero r_symndx relocs
Fix SH gas testsuite invalid assembly exposed by ec9ab52c
fixes for PR ld/19263 and PR ld/19264 should go the 2.26 branch
GNU Tools Cauldron, 9-11 September 2016, Hebden Bridge UK.
Re: gold: addend issues in icf.cc:get_section_contents
Fwd: Inconsistent warning/error message by GCC while linking 32/64 bit binary/library
Invoke aout N_* macros with pointer to struct
Linker symbol resolution differences with LTO.
New failures in GAS testsuite
New failures with .debug_ranges test
Please add versoon 2.27 to target milestone in binutils bugzilla
PowerPC ifunc with local symbols
PR19323 memory allocation greater than 4G
Problem with building PDF documentation
Re: R_PPC64_ENTRY
Reorder some power9 insns
rl78: relaxation fixes
Re: SH FDPIC ABI spec/binutils and kernel conflict on flag definitions
Re: SPARC: nested static initialization
SRC-POTFILES.in update
tc-ppc.c md_apply_fix tidy
Trim unused params from aout adjust_sizes_and_vmas
Two binutils issues for x86_64-w64-mingw32 host using msys2
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