Re: [PATCH] x86/Intel: don't accept bogus instructions

["H.J. Lu" <hjl dot tools at gmail dot com>]

On Thu, Jun 30, 2016 at 4:38 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 30.06.16 at 13:18, <hjl.tools@gmail.com> wrote:
>> On Thu, Jun 30, 2016 at 3:34 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>> ... due to their last byte looking like a suffix, when after its
>>> stripping a matching instruction can be found. Since memory operand
>>> size specifiers in Intel mode get converted into suffix representation
>>> internally, we need to keep track of the actual mnemonic suffix which
>>> may have got trimmed off, and check its validity while looking for a
>>> matching template. I tripper over this quite some time again after
>>> support for AMD's SSE5 instructions got removed, as at that point some
>>> of the SSE5 mnemonics, other than expected, didn't fail to assemble.
>>> But the problem affects many more instructions, namely (almost) all
>>> MMX, SSE, and AVX ones as it looks. I don't think it makes sense to
>>> add a testcase covering all of them, nor do I think it makes sense to
>>> pick out some random examples for a new test case.
>>
>> Please open a bug report to show there is a problem.
>
> I don't see the point, but anyway: 20318.
>
> Jan
>

Please add this testcase:

.text
phadddb %xmm0, %xmm1
phadddd %xmm0, %xmm1
phadddl %xmm0, %xmm1
phadddld %xmm0, %xmm1
phadddq %xmm0, %xmm1
phaddds %xmm0, %xmm1
phadddw %xmm0, %xmm1
.intel_syntax noprefix
phadddb xmm0, xmm1
phadddd xmm0, xmm1
phadddl xmm0, xmm1
phadddld xmm0, xmm1
phadddq xmm0, xmm1
phaddds xmm0, xmm1
phadddw xmm0, xmm1

to your patch and run it with both --32 and --64.  All of them should fail.

Thanks.

-- 
H.J.