[PATCH 0/7] ARC: Change max instruction length to 64 bits

[Graham Markall <graham dot markall at embecosm dot com>]

The current handling for arc instructions longer than 32-bits is all
handled as a special case in both the assembler and disassembler.

The problem with this approach is that it leads to code duplication.
Selecting a long instruction should be exactly the same process as
selecting a short instruction, except over more bits. In both cases we
select based on bit comparison, and initial operand insertion and
extraction.

In the existing implementation, only some of the logic for selecting
instructions is duplicated from the short instruction case to the long
instruction case - in particular, iterating over candidate instructions
with the same mnemonic is only possible for short instructions. This
precludes the implementation of NPS-400 Accelerator instructions which
are 48- and 64-bits long and have multiple variants with different
operand lists.

Rather than attempting to duplicate the remaining logic from short
instructions to long instructions, this series of patches unifies both
the long and short instruction worlds, converting the core opcodes
library from being largely 32-bit focused, to being 64-bit focused.

This series includes patches that:

- Fix some instruction masks that were incorrect. These incorrect masks
  caused no problems in the existing implementation, but changes in some
  of the patches in this series highlighted the issue, so a correction
  to these masks is included first.
- Make a small change to print_insn_arc to swap highbyte and lowbyte,
  which were consistently used to mean the opposite of their names. This
  change is made here to make subsequent changes more logical.
- Convert the opcodes implementation and supporting functionality to
  operate on 64-bit instructions. The special-case handling and
  duplicated logic for instructions that were previously considered
  "long" is removed.
- Add an implementation of the dcmac instruction for NPS-400, which
  could not be implemented prior to the change to 64-bit opcodes since
  it has multiple variants with different operands that need to be
  iterated over to select the correct one.

All patches in the series have been tested and pass with ARC big- and
little-endian.

Andrew Burgess (2):
  arc/opcodes/nps400: Fix some instruction masks
  arc: Change max instruction length to 64-bits

Graham Markall (5):
  gas/arc: Replace short_insn flag with insn length field
  arc: Replace ARC_SHORT macro with arc_opcode_len function
  opcodes/arc: Make some macros 64-bit safe
  arc: Swap highbyte and lowbyte in print_insn_arc
  arc: Implement NPS-400 dcmac instruction

 gas/ChangeLog                    |  33 ++
 gas/config/tc-arc.c              | 214 +++-------
 gas/testsuite/gas/arc/nps400-9.d |  44 +++
 gas/testsuite/gas/arc/nps400-9.s |  51 +++
 include/ChangeLog                |  21 +
 include/opcode/arc.h             |  97 ++---
 opcodes/ChangeLog                |  56 +++
 opcodes/arc-dis.c                | 481 +++++++++--------------
 opcodes/arc-ext.c                |   2 +-
 opcodes/arc-ext.h                |   2 +-
 opcodes/arc-fxi.h                | 366 ++++++++---------
 opcodes/arc-nps400-tbl.h         |  99 ++++-
 opcodes/arc-opc.c                | 829 +++++++++++++++++----------------------
 13 files changed, 1105 insertions(+), 1190 deletions(-)
 create mode 100644 gas/testsuite/gas/arc/nps400-9.d
 create mode 100644 gas/testsuite/gas/arc/nps400-9.s

-- 
2.7.4