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[PATCH][AArch64] Add ARMv8.3 PACGA instruction
- From: Szabolcs Nagy <szabolcs dot nagy at arm dot com>
- To: Binutils <binutils at sourceware dot org>
- Cc: <nd at arm dot com>
- Date: Tue, 8 Nov 2016 10:11:39 +0000
- Subject: [PATCH][AArch64] Add ARMv8.3 PACGA instruction
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Add support for the ARMv8.3 PACGA instruction.
(generated files are not in the diff.)
include/
2016-11-08 Szabolcs Nagy <szabolcs.nagy@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
opcodes/
2016-11-08 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (arch64_opcode_table): Add pacga.
(AARCH64_OPERANDS): Add Rm_SP.
* aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas/
2016-11-08 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP.
(parse_operands): Likewise.
gas/testsuite/
2016-11-08 Szabolcs Nagy <szabolcs.nagy@arm.com>
* gas/aarch64/pac.s: Add pacga.
* gas/aarch64/pac.d: Add pacga.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 408fe28..e56d068 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4983,6 +4983,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP:
+ case AARCH64_OPND_Rm_SP:
case AARCH64_OPND_Fd:
case AARCH64_OPND_Fn:
case AARCH64_OPND_Fm:
@@ -5314,6 +5315,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP:
case AARCH64_OPND_SVE_Rn_SP:
+ case AARCH64_OPND_Rm_SP:
po_int_reg_or_fail (REG_TYPE_R_SP);
break;
diff --git a/gas/testsuite/gas/aarch64/pac.d b/gas/testsuite/gas/aarch64/pac.d
index 448e674..4efbd88 100644
--- a/gas/testsuite/gas/aarch64/pac.d
+++ b/gas/testsuite/gas/aarch64/pac.d
@@ -32,3 +32,5 @@ Disassembly of section \.text:
5c: dac13fe5 autdzb x5
60: dac143e5 xpaci x5
64: dac147e5 xpacd x5
+ 68: 9ac33041 pacga x1, x2, x3
+ 6c: 9adf3041 pacga x1, x2, sp
diff --git a/gas/testsuite/gas/aarch64/pac.s b/gas/testsuite/gas/aarch64/pac.s
index dd01682..88f43a8 100644
--- a/gas/testsuite/gas/aarch64/pac.s
+++ b/gas/testsuite/gas/aarch64/pac.s
@@ -32,3 +32,6 @@
xpaci x5
xpacd x5
+
+ pacga x1, x2, x3
+ pacga x1, x2, sp
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 6cda660..a25b211 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -140,6 +140,7 @@ enum aarch64_opnd
AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
+ AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
AARCH64_OPND_PAIRREG, /* Paired register operand. */
AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 8e89b5b..f00549c 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2989,6 +2989,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_Rd_SP:
case AARCH64_OPND_Rn_SP:
case AARCH64_OPND_SVE_Rn_SP:
+ case AARCH64_OPND_Rm_SP:
assert (opnd->qualifier == AARCH64_OPND_QLF_W
|| opnd->qualifier == AARCH64_OPND_QLF_WSP
|| opnd->qualifier == AARCH64_OPND_QLF_X
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 97522d6..f4c0bd1 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2694,6 +2694,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
CORE_INSN ("rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS),
CORE_INSN ("ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
+ V8_3_INSN ("pacga", 0x9ac03000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm_SP), QL_I3SAMEX, 0),
/* CRC instructions. */
_CRC_INSN ("crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0),
_CRC_INSN ("crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0),
@@ -3987,6 +3988,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
"an integer or stack pointer register") \
Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \
"an integer or stack pointer register") \
+ Y(INT_REG, regno, "Rm_SP", OPD_F_MAYBE_SP, F(FLD_Rm), \
+ "an integer or stack pointer register") \
X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \
"the second reg of a pair") \
Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \