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Re: [PATCH, committed] X86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode
On Thu, Nov 3, 2016 at 10:14 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 03.11.16 at 17:57, <hjl.tools@gmail.com> wrote:
>> I checked in this patch to reuse opcode 0x80 decoder for opcode 0x82.
>
> Thanks!
>
> Jan
>
I checked in this to update opcode-suffix.d.
--
H.J.
---
commit 7766fd10024dc0587838fbc4608f3f8e30e17a26
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Wed Nov 9 12:11:50 2016 -0800
X86: Update opcode-suffix.d
PR binutils/20754
* testsuite/gas/i386/opcode-suffix.d: Updated.
diff --git a/gas/ChangeLog b/gas/ChangeLog
index e8481a3..1685c86 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20754
+ * testsuite/gas/i386/opcode-suffix.d: Updated.
+
2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/20775
diff --git a/gas/testsuite/gas/i386/opcode-suffix.d
b/gas/testsuite/gas/i386/opcode-suffix.d
index 74e0adb..a5c76a3 100644
--- a/gas/testsuite/gas/i386/opcode-suffix.d
+++ b/gas/testsuite/gas/i386/opcode-suffix.d
@@ -592,4 +592,12 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnpl -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovpw -0x6f6f6f70\(%eax\),%dx
[ ]*[a-f0-9]+: 66 0f 4b 90 90 90 90 90 cmovnpw -0x6f6f6f70\(%eax\),%dx
+ +[a-f0-9]+: 82 c3 01 addb \$0x1,%bl
+ +[a-f0-9]+: 82 f3 01 xorb \$0x1,%bl
+ +[a-f0-9]+: 82 d3 01 adcb \$0x1,%bl
+ +[a-f0-9]+: 82 db 01 sbbb \$0x1,%bl
+ +[a-f0-9]+: 82 e3 01 andb \$0x1,%bl
+ +[a-f0-9]+: 82 eb 01 subb \$0x1,%bl
+ +[a-f0-9]+: 82 f3 01 xorb \$0x1,%bl
+ +[a-f0-9]+: 82 fb 01 cmpb \$0x1,%bl
#pass