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Re: [committed, PATCH] Add support for Intel CET instructions
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>
- Cc: <binutils at sourceware dot org>
- Date: Tue, 07 Mar 2017 01:59:09 -0700
- Subject: Re: [committed, PATCH] Add support for Intel CET instructions
- Authentication-results: sourceware.org; auth=none
- References: <20170306232856.GA29545@intel.com>
>>> On 07.03.17 at 00:28, <hongjiu.lu@intel.com> wrote:
> Support Intel Control-flow Enforcement Technology (CET) instructions:
>
> https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enfo
> rcement-technology-preview.pdf
>
> gas/
>
> * config/tc-i386.c (cpu_arch): Add .cet.
> * doc/c-i386.texi: Document cet.
> * testsuite/gas/i386/cet-intel.d: New file.
> * testsuite/gas/i386/cet.d: Likewise.
> * testsuite/gas/i386/cet.s: Likewise.
> * testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
> * testsuite/gas/i386/x86-64-cet.d: Likewise.
> * testsuite/gas/i386/x86-64-cet.s: Likewise.
> * testsuite/gas/i386/i386.exp: Run Intel CET tests.
>
> opcodes/
>
> * i386-dis.c (REG_0F1E_MOD_3): New enum.
> (MOD_0F1E_PREFIX_1): Likewise.
> (MOD_0F38F5_PREFIX_2): Likewise.
> (MOD_0F38F6_PREFIX_0): Likewise.
> (RM_0F1E_MOD_3_REG_7): Likewise.
> (PREFIX_MOD_0_0F01_REG_5): Likewise.
> (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
> (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
> (PREFIX_0F1E): Likewise.
> (PREFIX_MOD_0_0FAE_REG_5): Likewise.
> (PREFIX_0F38F5): Likewise.
> (dis386_twobyte): Use PREFIX_0F1E.
> (reg_table): Add REG_0F1E_MOD_3.
> (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
> PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
> PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
> PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
> (three_byte_table): Use PREFIX_0F38F5.
> (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
> Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
> (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
> RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
> PREFIX_MOD_3_0F01_REG_5_RM_2.
> * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
> (cpu_flags): Add CpuCET.
> * i386-opc.h (CpuCET): New enum.
> (CpuUnused): Commented out.
> (i386_cpu_flags): Add cpucet.
> * i386-opc.tbl: Add Intel CET instructions.
> * i386-init.h: Regenerated.
> * i386-tbl.h: Likewise.
> ---
> gas/ChangeLog | 12 +
> gas/config/tc-i386.c | 2 +
> gas/doc/c-i386.texi | 2 +
> gas/testsuite/gas/i386/cet-intel.d | 31 ++
> gas/testsuite/gas/i386/cet.d | 29 ++
> gas/testsuite/gas/i386/cet.s | 25 +
> gas/testsuite/gas/i386/i386.exp | 4 +
> gas/testsuite/gas/i386/x86-64-cet-intel.d | 38 ++
> gas/testsuite/gas/i386/x86-64-cet.d | 37 ++
> gas/testsuite/gas/i386/x86-64-cet.s | 33 ++
> opcodes/ChangeLog | 34 ++
> opcodes/i386-dis.c | 105 ++++-
> opcodes/i386-gen.c | 3 +
> opcodes/i386-init.h | 119 ++---
> opcodes/i386-opc.h | 5 +
> opcodes/i386-opc.tbl | 19 +
> opcodes/i386-tbl.h | 730 +++++++++++++++++++-----------
> 17 files changed, 894 insertions(+), 334 deletions(-)
> create mode 100644 gas/testsuite/gas/i386/cet-intel.d
> create mode 100644 gas/testsuite/gas/i386/cet.d
> create mode 100644 gas/testsuite/gas/i386/cet.s
> create mode 100644 gas/testsuite/gas/i386/x86-64-cet-intel.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-cet.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-cet.s
>
> diff --git a/gas/ChangeLog b/gas/ChangeLog
> index 654b3cb..f9af65d6 100644
> --- a/gas/ChangeLog
> +++ b/gas/ChangeLog
> @@ -1,5 +1,17 @@
> 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
>
> + * config/tc-i386.c (cpu_arch): Add .cet.
> + * doc/c-i386.texi: Document cet.
> + * testsuite/gas/i386/cet-intel.d: New file.
> + * testsuite/gas/i386/cet.d: Likewise.
> + * testsuite/gas/i386/cet.s: Likewise.
> + * testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
> + * testsuite/gas/i386/x86-64-cet.d: Likewise.
> + * testsuite/gas/i386/x86-64-cet.s: Likewise.
> + * testsuite/gas/i386/i386.exp: Run Intel CET tests.
> +
> +2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
> +
> * testsuite/gas/i386/x86-64-mpx-inval-2.s: Force a good alignment.
> * testsuite/gas/i386/x86-64-mpx-inval-2.l: Expect [0-9A-F]+.
>
> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
> index 12b3032..7deacad 100644
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -978,6 +978,8 @@ static const arch_entry cpu_arch[] =
> CPU_RDPID_FLAGS, 0 },
> { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
> CPU_PTWRITE_FLAGS, 0 },
> + { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
> + CPU_CET_FLAGS, 0 },
> };
>
> static const noarch_entry cpu_noarch[] =
> diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
> index 2cbffb9..0733587 100644
> --- a/gas/doc/c-i386.texi
> +++ b/gas/doc/c-i386.texi
> @@ -167,6 +167,7 @@ accept various extension mnemonics. For example,
> @code{sha},
> @code{rdpid},
> @code{ptwrite},
> +@code{cet},
> @code{prefetchwt1},
> @code{clflushopt},
> @code{se1},
> @@ -1198,6 +1199,7 @@ supported on the CPU specified. The choices for
> @var{cpu_type} are:
> @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab
> @samp{.avx512ifma}
> @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab
> @samp{.avx512_4vnniw}
> @item @samp{.avx512_vpopcntdq} @tab @samp{.clwb} @tab @samp{.rdpid} @tab
> @samp{.ptwrite}
> +@item @samp{.cet}
> @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab
> @samp{.sse5}
> @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab
> @samp{.abm}
> @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
> diff --git a/gas/testsuite/gas/i386/cet-intel.d
> b/gas/testsuite/gas/i386/cet-intel.d
> new file mode 100644
> index 0000000..a5f5533
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/cet-intel.d
> @@ -0,0 +1,31 @@
> +#source: cet.s
> +#as: -J
> +#objdump: -dw -Mintel
> +#name: i386 CET (Intel mode)
> +
> +.*: +file format .*
> +
> +Disassembly of section .text:
> +
> +0+ <_start>:
> + +[a-f0-9]+: f3 0f 01 e9 incsspd
> + +[a-f0-9]+: f3 0f 1e c9 rdsspd ecx
> + +[a-f0-9]+: f3 0f 01 ea savessp
> + +[a-f0-9]+: f3 0f 01 29 rstorssp QWORD PTR \[ecx\]
> + +[a-f0-9]+: 0f 38 f6 04 02 wrssd \[edx\+eax\*1\],eax
> + +[a-f0-9]+: 66 0f 38 f5 14 2f wrussd \[edi\+ebp\*1\],edx
> + +[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[eax\]
> + +[a-f0-9]+: f3 0f ae 34 04 clrssbsy QWORD PTR \[esp\+eax\*1\]
> + +[a-f0-9]+: f3 0f 1e fa endbr64
> + +[a-f0-9]+: f3 0f 1e fb endbr32
> + +[a-f0-9]+: f3 0f 01 e9 incsspd
> + +[a-f0-9]+: f3 0f 1e c9 rdsspd ecx
> + +[a-f0-9]+: f3 0f 01 ea savessp
> + +[a-f0-9]+: f3 0f 01 2c 01 rstorssp QWORD PTR \[ecx\+eax\*1\]
> + +[a-f0-9]+: 0f 38 f6 02 wrssd \[edx\],eax
> + +[a-f0-9]+: 66 0f 38 f5 14 2f wrussd \[edi\+ebp\*1\],edx
> + +[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[eax\]
> + +[a-f0-9]+: f3 0f ae 34 04 clrssbsy QWORD PTR \[esp\+eax\*1\]
> + +[a-f0-9]+: f3 0f 1e fa endbr64
> + +[a-f0-9]+: f3 0f 1e fb endbr32
> +#pass
> diff --git a/gas/testsuite/gas/i386/cet.d b/gas/testsuite/gas/i386/cet.d
> new file mode 100644
> index 0000000..bb356e4
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/cet.d
> @@ -0,0 +1,29 @@
> +#objdump: -dw
> +#name: i386 CET
> +
> +.*: file format .*
> +
> +Disassembly of section .text:
> +
> +0+ <_start>:
> + +[a-f0-9]+: f3 0f 01 e9 incsspd
> + +[a-f0-9]+: f3 0f 1e c9 rdsspd %ecx
> + +[a-f0-9]+: f3 0f 01 ea savessp
> + +[a-f0-9]+: f3 0f 01 29 rstorssp \(%ecx\)
> + +[a-f0-9]+: 0f 38 f6 04 02 wrssd %eax,\(%edx,%eax,1\)
> + +[a-f0-9]+: 66 0f 38 f5 14 2f wrussd %edx,\(%edi,%ebp,1\)
> + +[a-f0-9]+: f3 0f ae 28 setssbsy \(%eax\)
> + +[a-f0-9]+: f3 0f ae 34 04 clrssbsy \(%esp,%eax,1\)
> + +[a-f0-9]+: f3 0f 1e fa endbr64
> + +[a-f0-9]+: f3 0f 1e fb endbr32
> + +[a-f0-9]+: f3 0f 01 e9 incsspd
> + +[a-f0-9]+: f3 0f 1e c9 rdsspd %ecx
> + +[a-f0-9]+: f3 0f 01 ea savessp
> + +[a-f0-9]+: f3 0f 01 2c 01 rstorssp \(%ecx,%eax,1\)
> + +[a-f0-9]+: 0f 38 f6 02 wrssd %eax,\(%edx\)
> + +[a-f0-9]+: 66 0f 38 f5 14 2f wrussd %edx,\(%edi,%ebp,1\)
> + +[a-f0-9]+: f3 0f ae 28 setssbsy \(%eax\)
> + +[a-f0-9]+: f3 0f ae 34 04 clrssbsy \(%esp,%eax,1\)
> + +[a-f0-9]+: f3 0f 1e fa endbr64
> + +[a-f0-9]+: f3 0f 1e fb endbr32
> +#pass
> diff --git a/gas/testsuite/gas/i386/cet.s b/gas/testsuite/gas/i386/cet.s
> new file mode 100644
> index 0000000..deb659d
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/cet.s
> @@ -0,0 +1,25 @@
> +# Check CET instructions
> + .text
> +_start:
> + incsspd
> + rdsspd %ecx
> + savessp
> + rstorssp (%ecx)
> + wrssd %eax, (%edx, %eax)
> + wrussd %edx, (%edi, %ebp)
> + setssbsy (%eax)
> + clrssbsy (%esp, %eax)
> + endbr64
> + endbr32
> +
> + .intel_syntax noprefix
> + incsspd
> + rdsspd ecx
> + savessp
> + rstorssp QWORD PTR [ecx + eax]
> + wrssd [edx],eax
> + wrussd [edi + ebp],edx
> + setssbsy QWORD PTR [eax]
> + clrssbsy QWORD PTR [esp + eax]
> + endbr64
> + endbr32
> diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
> index 10fe71c..cc5917a 100644
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -382,6 +382,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) &&
> [gas_32_check]]
> run_list_test "avx512vl-1" "-al"
> run_list_test "avx512vl-2" "-al"
> run_dump_test "fpu-bad"
> + run_dump_test "cet"
> + run_dump_test "cet-intel"
>
> # These tests require support for 8 and 16 bit relocs,
> # so we only run them for ELF and COFF targets.
> @@ -799,6 +801,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) &&
> [gas_64_check]] t
> run_list_test "x86-64-avx512vl-1" "-al"
> run_list_test "x86-64-avx512vl-2" "-al"
> run_dump_test "x86-64-opcode-bad"
> + run_dump_test "x86-64-cet"
> + run_dump_test "x86-64-cet-intel"
>
> if { ![istarget "*-*-aix*"]
> && ![istarget "*-*-beos*"]
> diff --git a/gas/testsuite/gas/i386/x86-64-cet-intel.d
> b/gas/testsuite/gas/i386/x86-64-cet-intel.d
> new file mode 100644
> index 0000000..07e666f
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-cet-intel.d
> @@ -0,0 +1,38 @@
> +#source: x86-64-cet.s
> +#objdump: -dw -Mintel
> +#name: x86-64 CET (Intel mode)
> +
> +.*: +file format .*
> +
> +Disassembly of section .text:
> +
> +0+ <_start>:
> + +[a-f0-9]+: f3 0f 01 e9 incsspd
> + +[a-f0-9]+: f3 48 0f 01 e9 incsspq
> + +[a-f0-9]+: f3 41 0f 1e cc rdsspd r12d
> + +[a-f0-9]+: f3 48 0f 1e c8 rdsspq rax
> + +[a-f0-9]+: f3 0f 01 ea savessp
> + +[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp QWORD PTR \[r12\]
> + +[a-f0-9]+: 41 0f 38 f6 04 24 wrssd \[r12\],eax
> + +[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq \[rcx\+r15\*1\],rdx
> + +[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd \[r12\],eax
> + +[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq \[rbx\+rax\*1\],rcx
> + +[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[rax\]
> + +[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy QWORD PTR \[rsi\+r12\*1\]
> + +[a-f0-9]+: f3 0f 1e fa endbr64
> + +[a-f0-9]+: f3 0f 1e fb endbr32
> + +[a-f0-9]+: f3 0f 01 e9 incsspd
> + +[a-f0-9]+: f3 48 0f 01 e9 incsspq
> + +[a-f0-9]+: f3 41 0f 1e cc rdsspd r12d
> + +[a-f0-9]+: f3 48 0f 1e c8 rdsspq rax
> + +[a-f0-9]+: f3 0f 01 ea savessp
> + +[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp QWORD PTR \[r12\]
> + +[a-f0-9]+: 41 0f 38 f6 04 24 wrssd \[r12\],eax
> + +[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq \[rcx\+r15\*1\],rdx
> + +[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd \[r12\],eax
> + +[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq \[rbx\+rax\*1\],rcx
> + +[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[rax\]
> + +[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy QWORD PTR \[rsi\+r12\*1\]
> + +[a-f0-9]+: f3 0f 1e fa endbr64
> + +[a-f0-9]+: f3 0f 1e fb endbr32
> +#pass
> diff --git a/gas/testsuite/gas/i386/x86-64-cet.d
> b/gas/testsuite/gas/i386/x86-64-cet.d
> new file mode 100644
> index 0000000..7e5b717
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-cet.d
> @@ -0,0 +1,37 @@
> +#objdump: -dw
> +#name: x86-64 CET
> +
> +.*: +file format .*
> +
> +Disassembly of section .text:
> +
> +0+ <_start>:
> + +[a-f0-9]+: f3 0f 01 e9 incsspd
> + +[a-f0-9]+: f3 48 0f 01 e9 incsspq
> + +[a-f0-9]+: f3 41 0f 1e cc rdsspd %r12d
> + +[a-f0-9]+: f3 48 0f 1e c8 rdsspq %rax
> + +[a-f0-9]+: f3 0f 01 ea savessp
> + +[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp \(%r12\)
> + +[a-f0-9]+: 41 0f 38 f6 04 24 wrssd %eax,\(%r12\)
> + +[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq %rdx,\(%rcx,%r15,1\)
> + +[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd %eax,\(%r12\)
> + +[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq %rcx,\(%rbx,%rax,1\)
> + +[a-f0-9]+: f3 0f ae 28 setssbsy \(%rax\)
> + +[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy \(%rsi,%r12,1\)
> + +[a-f0-9]+: f3 0f 1e fa endbr64
> + +[a-f0-9]+: f3 0f 1e fb endbr32
> + +[a-f0-9]+: f3 0f 01 e9 incsspd
> + +[a-f0-9]+: f3 48 0f 01 e9 incsspq
> + +[a-f0-9]+: f3 41 0f 1e cc rdsspd %r12d
> + +[a-f0-9]+: f3 48 0f 1e c8 rdsspq %rax
> + +[a-f0-9]+: f3 0f 01 ea savessp
> + +[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp \(%r12\)
> + +[a-f0-9]+: 41 0f 38 f6 04 24 wrssd %eax,\(%r12\)
> + +[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq %rdx,\(%rcx,%r15,1\)
> + +[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd %eax,\(%r12\)
> + +[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq %rcx,\(%rbx,%rax,1\)
> + +[a-f0-9]+: f3 0f ae 28 setssbsy \(%rax\)
> + +[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy \(%rsi,%r12,1\)
> + +[a-f0-9]+: f3 0f 1e fa endbr64
> + +[a-f0-9]+: f3 0f 1e fb endbr32
> +#pass
> diff --git a/gas/testsuite/gas/i386/x86-64-cet.s
> b/gas/testsuite/gas/i386/x86-64-cet.s
> new file mode 100644
> index 0000000..15a28d7
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-cet.s
> @@ -0,0 +1,33 @@
> +# Check 64bit CET instructions
> + .text
> +_start:
> + incsspd
> + incsspq
> + rdsspd %r12d
> + rdsspq %rax
> + savessp
> + rstorssp (%r12)
> + wrssd %eax, (%r12)
> + wrssq %rdx, (%rcx, %r15)
> + wrussd %eax, (%r12)
> + wrussq %rcx, (%rbx, %rax)
> + setssbsy (%rax)
> + clrssbsy (%rsi, %r12)
> + endbr64
> + endbr32
> +
> + .intel_syntax noprefix
> + incsspd
> + incsspq
> + rdsspd r12d
> + rdsspq rax
> + savessp
> + rstorssp QWORD PTR [r12]
> + wrssd [r12],eax
> + wrssq [rcx+r15],rdx
> + wrussd [r12],eax
> + wrussq [rbx+rax],rcx
> + setssbsy QWORD PTR [rax]
> + clrssbsy QWORD PTR [rsi+r12]
> + endbr64
> + endbr32
> diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
> index 27f3235..f2b1bec 100644
> --- a/opcodes/ChangeLog
> +++ b/opcodes/ChangeLog
> @@ -1,3 +1,37 @@
> +2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
> +
> + * i386-dis.c (REG_0F1E_MOD_3): New enum.
> + (MOD_0F1E_PREFIX_1): Likewise.
> + (MOD_0F38F5_PREFIX_2): Likewise.
> + (MOD_0F38F6_PREFIX_0): Likewise.
> + (RM_0F1E_MOD_3_REG_7): Likewise.
> + (PREFIX_MOD_0_0F01_REG_5): Likewise.
> + (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
> + (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
> + (PREFIX_0F1E): Likewise.
> + (PREFIX_MOD_0_0FAE_REG_5): Likewise.
> + (PREFIX_0F38F5): Likewise.
> + (dis386_twobyte): Use PREFIX_0F1E.
> + (reg_table): Add REG_0F1E_MOD_3.
> + (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
> + PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
> + PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
> + PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
> + (three_byte_table): Use PREFIX_0F38F5.
> + (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
> + Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
> + (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
> + RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
> + PREFIX_MOD_3_0F01_REG_5_RM_2.
> + * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
> + (cpu_flags): Add CpuCET.
> + * i386-opc.h (CpuCET): New enum.
> + (CpuUnused): Commented out.
> + (i386_cpu_flags): Add cpucet.
> + * i386-opc.tbl: Add Intel CET instructions.
> + * i386-init.h: Regenerated.
> + * i386-tbl.h: Likewise.
> +
> 2017-03-06 Alan Modra <amodra@gmail.com>
>
> PR 21124
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
> index 76781a0..3980c46 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -723,6 +723,7 @@ enum
> REG_0F01,
> REG_0F0D,
> REG_0F18,
> + REG_0F1E_MOD_3,
> REG_0F71,
> REG_0F72,
> REG_0F73,
> @@ -776,6 +777,7 @@ enum
> MOD_0F1A_PREFIX_0,
> MOD_0F1B_PREFIX_0,
> MOD_0F1B_PREFIX_1,
> + MOD_0F1E_PREFIX_1,
> MOD_0F24,
> MOD_0F26,
> MOD_0F2B_PREFIX_0,
> @@ -814,6 +816,8 @@ enum
> MOD_0FE7_PREFIX_2,
> MOD_0FF0_PREFIX_3,
> MOD_0F382A_PREFIX_2,
> + MOD_0F38F5_PREFIX_2,
> + MOD_0F38F6_PREFIX_0,
> MOD_62_32BIT,
> MOD_C4_32BIT,
> MOD_C5_32BIT,
> @@ -933,6 +937,7 @@ enum
> RM_0F01_REG_3,
> RM_0F01_REG_5,
> RM_0F01_REG_7,
> + RM_0F1E_MOD_3_REG_7,
> RM_0FAE_REG_5,
> RM_0FAE_REG_6,
> RM_0FAE_REG_7
> @@ -941,12 +946,16 @@ enum
> enum
> {
> PREFIX_90 = 0,
> + PREFIX_MOD_0_0F01_REG_5,
> + PREFIX_MOD_3_0F01_REG_5_RM_1,
> + PREFIX_MOD_3_0F01_REG_5_RM_2,
> PREFIX_0F10,
> PREFIX_0F11,
> PREFIX_0F12,
> PREFIX_0F16,
> PREFIX_0F1A,
> PREFIX_0F1B,
> + PREFIX_0F1E,
> PREFIX_0F2A,
> PREFIX_0F2B,
> PREFIX_0F2C,
> @@ -985,6 +994,7 @@ enum
> PREFIX_0FAE_REG_3,
> PREFIX_MOD_0_0FAE_REG_4,
> PREFIX_MOD_3_0FAE_REG_4,
> + PREFIX_MOD_0_0FAE_REG_5,
> PREFIX_0FAE_REG_6,
> PREFIX_0FAE_REG_7,
> PREFIX_0FB8,
> @@ -1048,6 +1058,7 @@ enum
> PREFIX_0F38DF,
> PREFIX_0F38F0,
> PREFIX_0F38F1,
> + PREFIX_0F38F5,
> PREFIX_0F38F6,
> PREFIX_0F3A08,
> PREFIX_0F3A09,
> @@ -2839,7 +2850,7 @@ static const struct dis386 dis386_twobyte[] = {
> { PREFIX_TABLE (PREFIX_0F1B) },
> { "nopQ", { Ev }, 0 },
> { "nopQ", { Ev }, 0 },
> - { "nopQ", { Ev }, 0 },
> + { PREFIX_TABLE (PREFIX_0F1E) },
> { "nopQ", { Ev }, 0 },
> /* 20 */
> { "movZ", { Rm, Cm }, 0 },
> @@ -3589,6 +3600,17 @@ static const struct dis386 reg_table[][8] = {
> { MOD_TABLE (MOD_0F18_REG_6) },
> { MOD_TABLE (MOD_0F18_REG_7) },
> },
> + /* REG_0F1E_MOD_3 */
> + {
> + { "nopQ", { Ev }, 0 },
> + { "rdsspK", { Rdq }, PREFIX_OPCODE },
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
> + },
> /* REG_0F71 */
> {
> { Bad_Opcode },
> @@ -3758,6 +3780,24 @@ static const struct dis386 prefix_table[][4] = {
> { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
> },
>
> + /* PREFIX_MOD_0_0F01_REG_5 */
> + {
> + { Bad_Opcode },
> + { "rstorssp", { Mq }, PREFIX_OPCODE },
> + },
> +
> + /* PREFIX_MOD_3_0F01_REG_5_RM_1 */
> + {
> + { Bad_Opcode },
> + { "incsspK", { Skip_MODRM }, PREFIX_OPCODE },
> + },
> +
> + /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
> + {
> + { Bad_Opcode },
> + { "savessp", { Skip_MODRM }, PREFIX_OPCODE },
> + },
> +
> /* PREFIX_0F10 */
> {
> { "movups", { XM, EXx }, PREFIX_OPCODE },
> @@ -3805,6 +3845,14 @@ static const struct dis386 prefix_table[][4] = {
> { "bndcn", { Gbnd, Ev_bnd }, 0 },
> },
>
> + /* PREFIX_0F1E */
> + {
> + { "nopQ", { Ev }, PREFIX_OPCODE },
> + { MOD_TABLE (MOD_0F1E_PREFIX_1) },
> + { "nopQ", { Ev }, PREFIX_OPCODE },
> + { "nopQ", { Ev }, PREFIX_OPCODE },
> + },
> +
> /* PREFIX_0F2A */
> {
> { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
> @@ -4080,11 +4128,17 @@ static const struct dis386 prefix_table[][4] = {
> { "ptwrite%LQ", { Edq }, 0 },
> },
>
> + /* PREFIX_MOD_0_0FAE_REG_5 */
> + {
> + { "xrstor", { FXSAVE }, PREFIX_OPCODE },
> + { "setssbsy", { Mq }, PREFIX_OPCODE },
> + },
> +
> /* PREFIX_0FAE_REG_6 */
> {
> - { "xsaveopt", { FXSAVE }, 0 },
> - { Bad_Opcode },
> - { "clwb", { Mb }, 0 },
> + { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
> + { "clrssbsy", { Mq }, PREFIX_OPCODE },
> + { "clwb", { Mb }, PREFIX_OPCODE },
> },
>
> /* PREFIX_0FAE_REG_7 */
> @@ -4513,9 +4567,16 @@ static const struct dis386 prefix_table[][4] = {
> { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
> },
>
> - /* PREFIX_0F38F6 */
> + /* PREFIX_0F38F5 */
> {
> { Bad_Opcode },
> + { Bad_Opcode },
> + { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
> + },
> +
> + /* PREFIX_0F38F6 */
> + {
> + { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
> { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
> { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
> { Bad_Opcode },
> @@ -7246,7 +7307,7 @@ static const struct dis386 three_byte_table[][256] = {
> { Bad_Opcode },
> { Bad_Opcode },
> { Bad_Opcode },
> - { Bad_Opcode },
> + { PREFIX_TABLE (PREFIX_0F38F5) },
> { PREFIX_TABLE (PREFIX_0F38F6) },
> { Bad_Opcode },
> /* f8 */
> @@ -11406,7 +11467,7 @@ static const struct dis386 mod_table[][2] = {
> },
> {
> /* MOD_0F01_REG_5 */
> - { Bad_Opcode },
> + { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
> { RM_TABLE (RM_0F01_REG_5) },
> },
> {
> @@ -11480,6 +11541,11 @@ static const struct dis386 mod_table[][2] = {
> { "nopQ", { Ev }, 0 },
> },
> {
> + /* MOD_0F1E_PREFIX_1 */
> + { "nopQ", { Ev }, 0 },
> + { REG_TABLE (REG_0F1E_MOD_3) },
> + },
> + {
> /* MOD_0F24 */
> { Bad_Opcode },
> { "movL", { Rd, Td }, 0 },
> @@ -11587,7 +11653,7 @@ static const struct dis386 mod_table[][2] = {
> },
> {
> /* MOD_0FAE_REG_5 */
> - { "xrstor", { FXSAVE }, 0 },
> + { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
> { RM_TABLE (RM_0FAE_REG_5) },
> },
> {
> @@ -11656,6 +11722,14 @@ static const struct dis386 mod_table[][2] = {
> { "movntdqa", { XM, Mx }, 0 },
> },
> {
> + /* MOD_0F38F5_PREFIX_2 */
> + { "wrussK", { M, Gdq }, PREFIX_OPCODE },
> + },
> + {
> + /* MOD_0F38F6_PREFIX_0 */
> + { "wrssK", { M, Gdq }, PREFIX_OPCODE },
> + },
> + {
> /* MOD_62_32BIT */
> { "bound{S|}", { Gv, Ma }, 0 },
> { EVEX_TABLE (EVEX_0F) },
> @@ -12157,8 +12231,8 @@ static const struct dis386 rm_table[][8] = {
> {
> /* RM_0F01_REG_5 */
> { Bad_Opcode },
> - { Bad_Opcode },
> - { Bad_Opcode },
> + { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_1) },
> + { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
> { Bad_Opcode },
> { Bad_Opcode },
> { Bad_Opcode },
> @@ -12174,6 +12248,17 @@ static const struct dis386 rm_table[][8] = {
> { "clzero", { Skip_MODRM }, 0 },
> },
> {
> + /* RM_0F1E_MOD_3_REG_7 */
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
> + { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + { "nopQ", { Ev }, 0 },
> + },
> + {
> /* RM_0FAE_REG_5 */
> { "lfence", { Skip_MODRM }, 0 },
> },
> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
> index df17851..4736afa 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -263,6 +263,8 @@ static initializer cpu_flag_init[] =
> "CpuRDPID" },
> { "CPU_PTWRITE_FLAGS",
> "CpuPTWRITE" },
> + { "CPU_CET_FLAGS",
> + "CpuCET" },
> { "CPU_ANY_X87_FLAGS",
> "CPU_ANY_287_FLAGS|Cpu8087" },
> { "CPU_ANY_287_FLAGS",
> @@ -524,6 +526,7 @@ static bitfield cpu_flags[] =
> BITFIELD (CpuOSPKE),
> BITFIELD (CpuRDPID),
> BITFIELD (CpuPTWRITE),
> + BITFIELD (CpuCET),
> BITFIELD (CpuRegMMX),
> BITFIELD (CpuRegXMM),
> BITFIELD (CpuRegYMM),
> diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
> index 140235f..9e4355c 100644
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -208,6 +208,8 @@ enum
> CpuRDPID,
> /* PTWRITE instruction required */
> CpuPTWRITE,
> + /* CET instruction support required */
> + CpuCET,
> /* MMX register support required */
> CpuRegMMX,
> /* XMM register support required */
> @@ -233,7 +235,9 @@ enum
>
> /* If you get a compiler error for zero width of the unused field,
> comment it out. */
> +#if 0
> #define CpuUnused (CpuMax + 1)
> +#endif
>
> /* We can check if an instruction is available with array instead
> of bitfield. */
> @@ -329,6 +333,7 @@ typedef union i386_cpu_flags
> unsigned int cpuospke:1;
> unsigned int cpurdpid:1;
> unsigned int cpuptwrite:1;
> + unsigned int cpucet:1;
> unsigned int cpuregmmx:1;
> unsigned int cpuregxmm:1;
> unsigned int cpuregymm:1;
> diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
> index 163a4e4..4c259d5 100644
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -5996,3 +5996,22 @@ rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_
> ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
>
> // PTWRITE instructions end.
> +
> +// CET instructions.
> +
> +incsspd, 0, 0xf30f01e9, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
> +incsspq, 0, 0xf30f01e9, None, 3, CpuCET|Cpu64, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { 0 }
> +rdsspd, 1, 0xf30f1e, 0x1, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
> +rdsspq, 1, 0xf30f1e, 0x1, 2, CpuRDPID|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
> +savessp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
> +rstorssp, 1, 0xf30f01, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
> +wrssd, 2, 0x0f38f6, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
> +wrssq, 2, 0x0f38f6, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
> +wrussd, 2, 0x660f38f5, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
> +wrussq, 2, 0x660f38f5, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
I think using "d" suffixes here is rather inconsistent with all other
AT&T syntax GPR-accessing instructions - this suffix is strictly
Intel syntax outside of SIMD. Please seriously consider switching
to conventional AT&T suffix handling for these.
Jan