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[PATCH 6/7] RISC-V: Fix assembler for c.li, c.andi and c.addiw
- From: Palmer Dabbelt <palmer at dabbelt dot com>
- To: binutils at sourceware dot org
- To: Tristan Gingold <gingold at adacore dot com>
- Cc: Kito Cheng <kito dot cheng at gmail dot com>
- Date: Wed, 22 Mar 2017 16:04:07 -0700
- Subject: [PATCH 6/7] RISC-V: Fix assembler for c.li, c.andi and c.addiw
- Authentication-results: sourceware.org; auth=none
- References: <20170322230408.8885-1-palmer@dabbelt.com>
From: Kito Cheng <kito.cheng@gmail.com>
- They can accept 0 in imm field
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
<c.andi>: Likewise.
<c.addiw> Likewise.
---
gas/ChangeLog | 6 ++++++
gas/config/tc-riscv.c | 8 ++++++++
opcodes/ChangeLog | 6 ++++++
opcodes/riscv-opc.c | 6 +++---
4 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b6ad1ee..f680ac6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+
+ * config/tc-riscv.c (validate_riscv_insn): Add 'o' RVC immediate
+ encoding format, which can accept 0-valued immediates.
+ (riscv_ip): Likewise.
+
2017-03-02 Kuan-Lin Chen <rufus@andestech.com>
* config/tc-riscv.h (HWARD2_USE_FIXED_ADVANCE_PC): New define.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 4d28042..429ba2b 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -500,6 +500,7 @@ validate_riscv_insn (const struct riscv_opcode *opc)
case 'c': break; /* RS1, constrained to equal sp */
case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
+ case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
@@ -1321,6 +1322,13 @@ rvc_imm_done:
ip->insn_opcode |=
ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
goto rvc_imm_done;
+ case 'o':
+ if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
+ || imm_expr->X_op != O_constant
+ || !VALID_RVC_IMM (imm_expr->X_add_number))
+ break;
+ ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
+ goto rvc_imm_done;
case 'K':
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|| imm_expr->X_op != O_constant
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 83f2cc1..8f7e44c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+ * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
+ <c.andi>: Likewise.
+ <c.addiw> Likewise.
+
+2017-03-14 Kito Cheng <kito.cheng@gmail.com>
+
* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
2017-03-13 Andrew Waterman <andrew@sifive.com>
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index edbf2f6..2b18a1e 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -562,7 +562,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, 0 },
{"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 },
{"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 },
-{"c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
+{"c.li", "C", "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 },
{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 },
{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 },
@@ -574,8 +574,8 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.slli", "C", "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 },
{"c.srli", "C", "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 },
{"c.srai", "C", "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 },
-{"c.andi", "C", "Cs,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 },
-{"c.addiw", "64C", "d,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 },
+{"c.andi", "C", "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 },
+{"c.addiw", "64C", "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 },
{"c.addw", "64C", "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 },
{"c.subw", "64C", "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 },
{"c.ldsp", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 },
--
2.10.2