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Re: [PATCH] PowerPC VLE changes


Another one is related to VLE also:

diff -ruN binutils-2.28-orig/opcodes/ppc-opc.c binutils-2.28/opcodes/ppc-opc.c
--- binutils-2.28-orig/opcodes/ppc-opc.c    2017-03-02 11:23:54.000000000 +0300
+++ binutils-2.28/opcodes/ppc-opc.c    2017-04-04 13:27:48.125164587 +0300
@@ -6997,6 +6997,7 @@
 {"se_rfci",    C(9),        C_MASK,        PPCVLE,    0,        {}},
 {"se_rfdi",    C(10),        C_MASK,        PPCVLE,    0,        {}},
 {"se_rfmci",    C(11),        C_MASK, PPCRFMCI|PPCVLE, 0,        {}},
+{"se_rfgi",    C(12),        C_MASK,        PPCVLE,    0,        {}},
 {"se_not",    SE_R(0,2),    SE_R_MASK,    PPCVLE,    0,        {RX}},
 {"se_neg",    SE_R(0,3),    SE_R_MASK,    PPCVLE,    0,        {RX}},
 {"se_mflr",    SE_R(0,8),    SE_R_MASK,    PPCVLE,    0,        {RX}},
@@ -7154,6 +7155,7 @@
 {"e_btl",    EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0,        {BI32,B15}},

 {"e_cmph",    X(31,14),    X_MASK,        PPCVLE,    0,        {CRD, RA, RB}},
+{"e_sc",    X(31,36),    XRTRA_MASK,        PPCVLE,    0,        {ELEV}},
 {"e_cmphl",    X(31,46),    X_MASK,        PPCVLE,    0,        {CRD, RA, RB}},
 {"e_crandc",    XL(31,129),    XL_MASK,    PPCVLE,    0,        {BT, BA, BB}},
 {"e_crnand",    XL(31,225),    XL_MASK,    PPCVLE,    0,        {BT, BA, BB}},

On Tue, Apr 4, 2017 at 1:23 PM, Alexander Fedotov <alfedotov@gmail.com> wrote:
> Okay. Removed change about macro from patch. Kept only e200z4 instructions.
>
> diff -ruN binutils-2.28-orig/opcodes/ppc-opc.c binutils-2.28/opcodes/ppc-opc.c
> --- binutils-2.28-orig/opcodes/ppc-opc.c    2017-03-02 11:23:54.000000000 +0300
> +++ binutils-2.28/opcodes/ppc-opc.c    2017-04-04 13:21:36.789164587 +0300
> @@ -5762,7 +5762,7 @@
>  {"mcrxr",    X(31,512),    XBFRARB_MASK, COM,    POWER7,        {BF}},
>
>  {"lbdcbx",    X(31,514),    X_MASK,      E200Z4,    0,        {RT, RA, RB}},
> -{"lbdx",    X(31,515),    X_MASK,         E500MC,    0,        {RT, RA, RB}},
> +{"lbdx",    X(31,515),    X_MASK,         E500MC|E200Z4,    0,
> {RT, RA, RB}},
>
>  {"bblels",    X(31,518),    X_MASK,         PPCBRLK,    0,        {0}},
>
> @@ -5813,7 +5813,7 @@
>  {"maskir.",    XRC(31,541,1),    X_MASK,         M601,    0,
> {RA, RS, RB}},
>
>  {"lhdcbx",    X(31,546),    X_MASK,      E200Z4,    0,        {RT, RA, RB}},
> -{"lhdx",    X(31,547),    X_MASK,         E500MC,    0,        {RT, RA, RB}},
> +{"lhdx",    X(31,547),    X_MASK,         E500MC|E200Z4,    0,
> {RT, RA, RB}},
>
>  {"lvtrx",    X(31,549),    X_MASK,         PPCVEC2,    0,        {VD,
> RA0, RB}},
>
> @@ -5837,7 +5837,7 @@
>  {"mcrxrx",    X(31,576),     XBFRARB_MASK, POWER9,    0,        {BF}},
>
>  {"lwdcbx",    X(31,578),    X_MASK,      E200Z4,    0,        {RT, RA, RB}},
> -{"lwdx",    X(31,579),    X_MASK,         E500MC,    0,        {RT, RA, RB}},
> +{"lwdx",    X(31,579),    X_MASK,         E500MC|E200Z4,    0,
> {RT, RA, RB}},
>
>  {"lvtlx",    X(31,581),    X_MASK,         PPCVEC2,    0,        {VD,
> RA0, RB}},
>
> @@ -5888,7 +5888,7 @@
>  {"lfdux",    X(31,631),    X_MASK,         COM,    PPCEFS,
> {FRT, RAS, RB}},
>
>  {"stbdcbx",    X(31,642),    X_MASK,      E200Z4,    0,        {RS, RA, RB}},
> -{"stbdx",    X(31,643),    X_MASK,         E500MC,    0,        {RS, RA, RB}},
> +{"stbdx",    X(31,643),    X_MASK,         E500MC|E200Z4,    0,
>  {RS, RA, RB}},
>
>  {"stvlx",    X(31,647),    X_MASK,         CELL,    0,        {VS, RA0, RB}},
>  {"stbfcmux",    APU(31,647,0),    APU_MASK,    PPC405,    0,
> {FCRT, RA, RB}},
> @@ -5926,7 +5926,7 @@
>  {"sre.",    XRC(31,665,1),    X_MASK,         M601,    0,        {RA, RS, RB}},
>
>  {"sthdcbx",    X(31,674),    X_MASK,      E200Z4,    0,        {RS, RA, RB}},
> -{"sthdx",    X(31,675),    X_MASK,         E500MC,    0,        {RS, RA, RB}},
> +{"sthdx",    X(31,675),    X_MASK,         E500MC|E200Z4,    0,
>  {RS, RA, RB}},
>
>  {"stvfrx",    X(31,677),    X_MASK,         PPCVEC2,    0,
> {VS, RA0, RB}},
>
> @@ -5944,7 +5944,7 @@
>  {"sriq.",    XRC(31,696,1),    X_MASK,         M601,    0,
> {RA, RS, SH}},
>
>  {"stwdcbx",    X(31,706),    X_MASK,         E200Z4,    0,
> {RS, RA, RB}},
> -{"stwdx",    X(31,707),    X_MASK,         E500MC,    0,        {RS, RA, RB}},
> +{"stwdx",    X(31,707),    X_MASK,         E500MC|E200Z4,    0,
>  {RS, RA, RB}},
>
>  {"stvflx",    X(31,709),    X_MASK,         PPCVEC2,    0,
> {VS, RA0, RB}},
>
> On Tue, Apr 4, 2017 at 4:28 AM, Alan Modra <amodra@gmail.com> wrote:
>> On Wed, Mar 29, 2017 at 10:36:36PM +0300, Alexander Fedotov wrote:
>>> Well, I think while such aliases are not in PowerISA and may be
>>> changed in any moment - better to move such ones to macros table.
>>> Performance should not harm dramatically if at all.
>>>
>>> Anyway, don't miss decorated storage instruction for e200z4 from my patch.
>>
>> I don't like being a dictator since that tends to drive away
>> contributors, but let me make it absolutely clear.  I will not accept
>> a patch that moves insns to the powerpc macro table.  Since your patch
>> at https://sourceware.org/ml/binutils/2017-03/msg00348.html does that,
>> and lacks a ChangeLog entry, it is currently blocked.
>>
>> --
>> Alan Modra
>> Australia Development Lab, IBM
>
>
>
> --
> Best regards,
> AF



-- 
Best regards,
AF


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