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[committed 2/3] MIPS: Add microMIPS R5 support


Add base microMIPS Release 5 ISA support and the ERETNC instruction in 
particular, as per the architecture specifications[1][2].

Most of this change by Andrew Bennett.

References:

[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32 
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
    Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit 
    Instructions", pp. 266-267

[2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
    Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit 
    Instructions", pp. 326-327

	binutils/
	* NEWS: Mention microMIPS Release 5 ISA support.

	opcodes/
	* micromips-opc.c (I36): New macro.
	(micromips_opcodes): Add "eretnc".

	gas/
	* testsuite/gas/mips/micromips@r5.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new test.
---
binutils-umips-r5.diff
Index: binutils/binutils/NEWS
===================================================================
--- binutils.orig/binutils/NEWS	2017-06-30 05:20:33.271762207 +0100
+++ binutils/binutils/NEWS	2017-06-30 05:40:15.861633396 +0100
@@ -1,5 +1,8 @@
 -*- text -*-
 
+* The MIPS port now supports the microMIPS Release 5 ISA for assembly and
+  disassembly.
+
 * The MIPS port now supports the Imagination interAptiv MR2 processor,
   which implements the MIPS32r3 ISA, the MIPS16e2 ASE as well as a couple
   of implementation-specific regular MIPS and MIPS16e2 ASE instructions.
Index: binutils/gas/testsuite/gas/mips/micromips@r5.d
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ binutils/gas/testsuite/gas/mips/micromips@r5.d	2017-06-30 05:40:15.904897891 +0100
@@ -0,0 +1,9 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source: r5.s
+#name: Test MIPS32r5 instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0001f37c 	eretnc
+	\.\.\.
Index: binutils/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils.orig/gas/testsuite/gas/mips/mips.exp	2017-06-30 05:37:43.894690796 +0100
+++ binutils/gas/testsuite/gas/mips/mips.exp	2017-06-30 05:40:15.912035825 +0100
@@ -1565,7 +1565,7 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "xpa-err"	[mips_arch_list_matching mips32r2 !micromips]
     run_dump_test_arches "xpa-virt-err" \
 				[mips_arch_list_matching mips32r2 !micromips]
-    run_dump_test_arches "r5" "-32"	[mips_arch_list_matching mips32r5 !micromips]
+    run_dump_test_arches "r5" "-32"	[mips_arch_list_matching mips32r5]
 
     run_dump_test "pcrel-1"
     run_dump_test "pcrel-2"
Index: binutils/opcodes/micromips-opc.c
===================================================================
--- binutils.orig/opcodes/micromips-opc.c	2017-06-30 05:20:33.324609129 +0100
+++ binutils/opcodes/micromips-opc.c	2017-06-30 05:40:15.929241834 +0100
@@ -253,6 +253,7 @@ decode_micromips_operand (const char *p)
    are accepted as 64-bit microMIPS ISA.  */
 #define I1	INSN_ISA1
 #define I3	INSN_ISA3
+#define I36	INSN_ISA32R5
 
 /* MIPS DSP ASE support.  */
 #define WR_a	WR_HILO		/* Write DSP accumulators (reuse WR_HILO).  */
@@ -687,6 +688,7 @@ const struct mips_opcode micromips_opcod
 {"ei",			"",		0x0000577c, 0xffffffff,	WR_C0,			0,		I1,		0,	0 },
 {"ei",			"s",		0x0000577c, 0xffe0ffff,	WR_1|WR_C0,		0,		I1,		0,	0 },
 {"eret",		"",		0x0000f37c, 0xffffffff,	NODS,			0,		I1,		0,	0 },
+{"eretnc",		"",		0x0001f37c, 0xffffffff,	NODS,			0,		I36,		0,	0 },
 {"ext",			"t,r,+A,+C",	0x0000002c, 0xfc00003f, WR_1|RD_2,		0,		I1,		0,	0 },
 {"floor.l.d",		"T,V",		0x5400433b, 0xfc00ffff,	WR_1|RD_2|FP_D,		0,		I1,		0,	0 },
 {"floor.l.s",		"T,V",		0x5400033b, 0xfc00ffff,	WR_1|RD_2|FP_S|FP_D,	0,		I1,		0,	0 },


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