This is the mail archive of the binutils@sourceware.org mailing list for the binutils project.

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]
Other format:	[Raw text]

[ARM, gas] Don't warn on REG_SP when used in CRC32 instructions

From: Jiong Wang <jiong dot wang at foss dot arm dot com>
To: Binutils <binutils at sourceware dot org>
Date: Wed, 9 Aug 2017 16:01:50 +0100
Subject: [ARM, gas] Don't warn on REG_SP when used in CRC32 instructions
Authentication-results: sourceware.org; auth=none

Hi,

  According to ARMv8-A architecture manual, REG_SP is allowed in CRC32 instructions
in Thumb mode.  It is REG_PC that will cause unpredictable behaviours on both ARM
and Thumb.

  This patch removes the incorrect warning on Thumb mode.

  Meanwhile the disassembler is updated to use format "<bitfield>R" instead of
"<bitfield>S".  "<bitfield>S" is not used elsewhere. so I have deleted related
code from the disassembler.

  cross and native gas check OK.

  OK for master and backport to 2.28 and 2.29?

  Thanks.

2017-08-09  Jiong Wang  <jiong.wang@arm.com>

opcodes/
	* arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
	register operands in CRC instructions.
	(print_insn_thumb32): Remove "<bitfield>S" support.  Updated the
	comments.

gas/
	* config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode.
	* testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result.
	* testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise
	* testsuite/gas/arm/crc32-armv8-a.d: Likewise
	* testsuite/gas/arm/crc32-armv8-r.d: Likewise
	* testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case.
	* testsuite/gas/arm/crc32-armv8-ar.s: Likewise
	* testsuite/gas/arm/crc32-bad.l: Update expected error message.

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index a885efe4fce127e6608c658361932b2f82af7e30..412102f612f8cd3b4220ab80eba5ef6ad7100302 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -17598,8 +17598,6 @@ do_crc32_1 (unsigned int poly, unsigned int sz)
 
   if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
     as_warn (UNPRED_REG ("r15"));
-  if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
-    as_warn (UNPRED_REG ("r13"));
 }
 
 static void
diff --git a/gas/testsuite/gas/arm/crc32-armv8-a-bad.d b/gas/testsuite/gas/arm/crc32-armv8-a-bad.d
index 18d48444895ac068500eec3a7d0225fa76f88be6..bc559e018e179118d9f105517679b01e32d3513f 100644
--- a/gas/testsuite/gas/arm/crc32-armv8-a-bad.d
+++ b/gas/testsuite/gas/arm/crc32-armv8-a-bad.d
@@ -15,9 +15,9 @@ Disassembly of section .text:
 0+c <[^>]*> e10f0242 	crc32cb	r0, pc, r2	; <UNPREDICTABLE>
 0+10 <[^>]*> e121f242 	crc32ch	pc, r1, r2	; <UNPREDICTABLE>
 0+14 <[^>]*> e14f0242 	crc32cw	r0, pc, r2	; <UNPREDICTABLE>
-0+18 <[^>]*> fac1 fd82 	crc32b	sp, r1, r2	; <UNPREDICTABLE>
+0+18 <[^>]*> fac1 ff82 	crc32b	pc, r1, r2	; <UNPREDICTABLE>
 0+1c <[^>]*> facf f092 	crc32h	r0, pc, r2	; <UNPREDICTABLE>
-0+20 <[^>]*> fac1 f0ad 	crc32w	r0, r1, sp	; <UNPREDICTABLE>
+0+20 <[^>]*> fac1 f0af 	crc32w	r0, r1, pc	; <UNPREDICTABLE>
 0+24 <[^>]*> fadf f082 	crc32cb	r0, pc, r2	; <UNPREDICTABLE>
-0+28 <[^>]*> fad1 fd92 	crc32ch	sp, r1, r2	; <UNPREDICTABLE>
+0+28 <[^>]*> fad1 ff92 	crc32ch	pc, r1, r2	; <UNPREDICTABLE>
 0+2c <[^>]*> fadf f0a2 	crc32cw	r0, pc, r2	; <UNPREDICTABLE>
diff --git a/gas/testsuite/gas/arm/crc32-armv8-a.d b/gas/testsuite/gas/arm/crc32-armv8-a.d
index b09942ed34e0b925f1de49f34b489a3f4ccba50c..1374553638b9132a47a9da65e922982869c039bf 100644
--- a/gas/testsuite/gas/arm/crc32-armv8-a.d
+++ b/gas/testsuite/gas/arm/crc32-armv8-a.d
@@ -20,4 +20,15 @@ Disassembly of section .text:
 0+24 <[^>]*> fad1 f082 	crc32cb	r0, r1, r2
 0+28 <[^>]*> fad1 f092 	crc32ch	r0, r1, r2
 0+2c <[^>]*> fad1 f0a2 	crc32cw	r0, r1, r2
-
+0+30 <[^>]*> e101d042 	crc32b	sp, r1, r2
+0+34 <[^>]*> e12db042 	crc32h	fp, sp, r2
+0+38 <[^>]*> e141004d 	crc32w	r0, r1, sp
+0+3c <[^>]*> e10d9242 	crc32cb	r9, sp, r2
+0+40 <[^>]*> e121d248 	crc32ch	sp, r1, r8
+0+44 <[^>]*> e141a24d 	crc32cw	sl, r1, sp
+0+48 <[^>]*> fac1 fc8d 	crc32b	ip, r1, sp
+0+4c <[^>]*> facd fa92 	crc32h	r5, sp, r2
+0+50 <[^>]*> fac1 fda7 	crc32w	sp, r1, r7
+0+54 <[^>]*> fadd f082 	crc32cb	r0, sp, r2
+0+58 <[^>]*> fad5 f09d 	crc32ch	r0, r5, sp
+0+5c <[^>]*> fad1 fda9 	crc32cw	sp, r1, r9
diff --git a/gas/testsuite/gas/arm/crc32-armv8-ar-bad.s b/gas/testsuite/gas/arm/crc32-armv8-ar-bad.s
index 4e497e3f3bdc13c87ab8a364aabe77ce3bdeab08..847156c215da538cdd2ced6dee3c69960c71bff1 100644
--- a/gas/testsuite/gas/arm/crc32-armv8-ar-bad.s
+++ b/gas/testsuite/gas/arm/crc32-armv8-ar-bad.s
@@ -9,9 +9,9 @@ crc32ch r15, r1, r2
 crc32cw r0, r15, r2
 
 .thumb
-crc32b r13, r1, r2
+crc32b r15, r1, r2
 crc32h r0, r15, r2
-crc32w r0, r1, r13
+crc32w r0, r1, r15
 crc32cb r0, r15, r2
-crc32ch r13, r1, r2
+crc32ch r15, r1, r2
 crc32cw r0, r15, r2
diff --git a/gas/testsuite/gas/arm/crc32-armv8-ar.s b/gas/testsuite/gas/arm/crc32-armv8-ar.s
index 63c1d68671ef168eb9025eeb59c403b18181af78..9a0edf7cd78e01a00301e558bf9ee27151289b77 100644
--- a/gas/testsuite/gas/arm/crc32-armv8-ar.s
+++ b/gas/testsuite/gas/arm/crc32-armv8-ar.s
@@ -15,3 +15,19 @@ crc32w r0, r1, r2
 crc32cb r0, r1, r2
 crc32ch r0, r1, r2
 crc32cw r0, r1, r2
+
+.arm
+crc32b sp, r1, r2
+crc32h r11, sp, r2
+crc32w r0, r1, sp
+crc32cb r9, sp, r2
+crc32ch sp, r1, r8
+crc32cw r10, r1, sp
+
+.thumb
+crc32b r12, r1, sp
+crc32h r10, sp, r2
+crc32w sp, r1, r7
+crc32cb r0, sp, r2
+crc32ch r0, r5, sp
+crc32cw sp, r1, r9
diff --git a/gas/testsuite/gas/arm/crc32-armv8-r-bad.d b/gas/testsuite/gas/arm/crc32-armv8-r-bad.d
index a1a4f61fe448c65eab0ff5b42db3c8b812b5c73d..4e6fe3ff767136a4ae9f1ee0370640eb4f459bfa 100644
--- a/gas/testsuite/gas/arm/crc32-armv8-r-bad.d
+++ b/gas/testsuite/gas/arm/crc32-armv8-r-bad.d
@@ -15,9 +15,9 @@ Disassembly of section .text:
 0+c <[^>]*> e10f0242 	crc32cb	r0, pc, r2	; <UNPREDICTABLE>
 0+10 <[^>]*> e121f242 	crc32ch	pc, r1, r2	; <UNPREDICTABLE>
 0+14 <[^>]*> e14f0242 	crc32cw	r0, pc, r2	; <UNPREDICTABLE>
-0+18 <[^>]*> fac1 fd82 	crc32b	sp, r1, r2	; <UNPREDICTABLE>
+0+18 <[^>]*> fac1 ff82 	crc32b	pc, r1, r2	; <UNPREDICTABLE>
 0+1c <[^>]*> facf f092 	crc32h	r0, pc, r2	; <UNPREDICTABLE>
-0+20 <[^>]*> fac1 f0ad 	crc32w	r0, r1, sp	; <UNPREDICTABLE>
+0+20 <[^>]*> fac1 f0af 	crc32w	r0, r1, pc	; <UNPREDICTABLE>
 0+24 <[^>]*> fadf f082 	crc32cb	r0, pc, r2	; <UNPREDICTABLE>
-0+28 <[^>]*> fad1 fd92 	crc32ch	sp, r1, r2	; <UNPREDICTABLE>
+0+28 <[^>]*> fad1 ff92 	crc32ch	pc, r1, r2	; <UNPREDICTABLE>
 0+2c <[^>]*> fadf f0a2 	crc32cw	r0, pc, r2	; <UNPREDICTABLE>
diff --git a/gas/testsuite/gas/arm/crc32-armv8-r.d b/gas/testsuite/gas/arm/crc32-armv8-r.d
index b1798213c3a19783e1cfd501d8cc58a664d86e9d..6918e071a8b00ae0679db319472ff97af0611829 100644
--- a/gas/testsuite/gas/arm/crc32-armv8-r.d
+++ b/gas/testsuite/gas/arm/crc32-armv8-r.d
@@ -20,4 +20,15 @@ Disassembly of section .text:
 0+24 <[^>]*> fad1 f082 	crc32cb	r0, r1, r2
 0+28 <[^>]*> fad1 f092 	crc32ch	r0, r1, r2
 0+2c <[^>]*> fad1 f0a2 	crc32cw	r0, r1, r2
-
+0+30 <[^>]*> e101d042 	crc32b	sp, r1, r2
+0+34 <[^>]*> e12db042 	crc32h	fp, sp, r2
+0+38 <[^>]*> e141004d 	crc32w	r0, r1, sp
+0+3c <[^>]*> e10d9242 	crc32cb	r9, sp, r2
+0+40 <[^>]*> e121d248 	crc32ch	sp, r1, r8
+0+44 <[^>]*> e141a24d 	crc32cw	sl, r1, sp
+0+48 <[^>]*> fac1 fc8d 	crc32b	ip, r1, sp
+0+4c <[^>]*> facd fa92 	crc32h	r5, sp, r2
+0+50 <[^>]*> fac1 fda7 	crc32w	sp, r1, r7
+0+54 <[^>]*> fadd f082 	crc32cb	r0, sp, r2
+0+58 <[^>]*> fad5 f09d 	crc32ch	r0, r5, sp
+0+5c <[^>]*> fad1 fda9 	crc32cw	sp, r1, r9
diff --git a/gas/testsuite/gas/arm/crc32-bad.l b/gas/testsuite/gas/arm/crc32-bad.l
index ea520aa9f2311662a339a85fc3840fb580b4ab75..01e1d22861bbad1346524cc3d307ef8ecd73a5f8 100644
--- a/gas/testsuite/gas/arm/crc32-bad.l
+++ b/gas/testsuite/gas/arm/crc32-bad.l
@@ -5,9 +5,9 @@
 [^:]*.s:7: Warning: using r15 results in unpredictable behaviour
 [^:]*.s:8: Warning: using r15 results in unpredictable behaviour
 [^:]*.s:9: Warning: using r15 results in unpredictable behaviour
-[^:]*.s:12: Warning: using r13 results in unpredictable behaviour
+[^:]*.s:12: Warning: using r15 results in unpredictable behaviour
 [^:]*.s:13: Warning: using r15 results in unpredictable behaviour
-[^:]*.s:14: Warning: using r13 results in unpredictable behaviour
+[^:]*.s:14: Warning: using r15 results in unpredictable behaviour
 [^:]*.s:15: Warning: using r15 results in unpredictable behaviour
-[^:]*.s:16: Warning: using r13 results in unpredictable behaviour
+[^:]*.s:16: Warning: using r15 results in unpredictable behaviour
 [^:]*.s:17: Warning: using r15 results in unpredictable behaviour
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 25000046d9fa5b2e4d20133c51eb22c998e0d60a..59a5978984cc1c1f4aba79993917befa5d141a28 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2699,7 +2699,6 @@ static const struct opcode16 thumb_opcodes[] =
        %<bitfield>W	print bitfield*4 in decimal
        %<bitfield>r	print bitfield as an ARM register
        %<bitfield>R	as %<>r but r15 is UNPREDICTABLE
-       %<bitfield>S	as %<>R but r13 is UNPREDICTABLE
        %<bitfield>c	print bitfield as a condition code
 
        %<bitfield>'c	print specified char iff bitfield is all ones
@@ -2767,17 +2766,17 @@ static const struct opcode32 thumb32_opcodes[] =
 
   /* CRC32 instructions.  */
   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
-    0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
+    0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
-    0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
+    0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
-    0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
+    0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
-    0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
+    0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
-    0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
+    0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
-    0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
+    0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
 
   /* V7 instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
@@ -5987,10 +5986,6 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 		      value_in_comment = val * 4;
 		      break;
 
-		    case 'S':
-		      if (val == 13)
-			is_unpredictable = TRUE;
-		      /* Fall through.  */
 		    case 'R':
 		      if (val == 15)
 			is_unpredictable = TRUE;

Follow-Ups:
- Re: [ARM, gas] Don't warn on REG_SP when used in CRC32 instructions
  - From: Nick Clifton

Index Nav:	[Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav:	[Date Prev] [Date Next]	[Thread Prev] [Thread Next]