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Re: [PATCH] [PowerPC] VLE update
>> If you split off the part dealing with SEC_PPC_VLE that can be
>> committed separately.
Done. New patch attached.
>> OK, but if there was a processor that could operate in both VLE and
>> non-VLE mode (controlled by MAS2 bit VLE), would these instructions be
>> available in both modes? If only VLE, then SHF_PPC_VLE ought to be
>> set for any section containing them. See tc-ppc.c:3513.
>>
>> However, from the fact that the "Lightweight Signal Processing APU
>> (LSP APU) Reference Manual" does not mention VLE, and the encoding of
>> these instructions, my guess is that these instruction are not VLE and
>> thus should not be in vle_opcodes.
Yes, there could be e.g e200z759n core. But it has SPE, not LSP.
On Tue, Aug 29, 2017 at 9:17 AM, Alan Modra <amodra@gmail.com> wrote:
> On Mon, Aug 28, 2017 at 05:20:45PM +0300, Alexander Fedotov wrote:
>> > You could reuse the SEC_MEP_VLIW bit, I guess. The section flags
>> > weren't really supposed to be used for target-specific purposes, but
>> > it seems pointless trying to be a purist now.
>>
>> Okay, so I will set
>> +#define SEC_PPC_VLE SEC_MEP_VLIW
>
> If you split off the part dealing with SEC_PPC_VLE that can be
> committed separately.
>
>> > That doesn't look elegant at all. So you are using R_PPC_PLTREL24 and
>> > R_PPC_LOCAL24PC relocations in VLE code but giving them a new meaning.
>> > Is that documented in the ABI?
>> >
>> > I think it would be better to define new R_PPC_VLE_PLTREL24 and
>> > R_PPC_VLE_LOCAL24 relocs, and make the assembler generate them when
>> > assembling VLE code.
>>
>> Nope, they are not defined by ABI at all. I agree it would be better
>> to rework. I will remove it from current patch set.
>
> I should note that I'm not greatly concerned about adding relocations
> that aren't described in an ABI document. It's not ideal, but the
> document can always be modified later. I was more concerned that
> someone may have already described R_PPC_PLTREL24 as behaving
> differently for VLE, and the problem that causes for compatibility if
> the GNU toolchain then goes off and implements something else.
>
>> > As I understand it, SHF_PPC_VLE and PF_PPC_VLE are set on sections or
>> > segments containing instructions that can only be executed by a
>> > processor in VLE mode. PPC_OPCODE_VLE is set for such opcodes too.
>> > So, do the LSP instructions only execute in VLE mode? I suspect not,
>> > from their encoding.
>> >
>> > Do you have the LSP instructions in the correct opcode table?
>>
>> I see that LSP instructions are available only on the cores with VLE ISA only.
>
> OK, but if there was a processor that could operate in both VLE and
> non-VLE mode (controlled by MAS2 bit VLE), would these instructions be
> available in both modes? If only VLE, then SHF_PPC_VLE ought to be
> set for any section containing them. See tc-ppc.c:3513.
>
> However, from the fact that the "Lightweight Signal Processing APU
> (LSP APU) Reference Manual" does not mention VLE, and the encoding of
> these instructions, my guess is that these instruction are not VLE and
> thus should not be in vle_opcodes.
>
> --
> Alan Modra
> Australia Development Lab, IBM
--
Best regards,
AF
From 7e445bda4bae1899527fe0d562dfd7f9654189a6 Mon Sep 17 00:00:00 2001
From: Alexander Fedotov-B55613 <b55613@freescale.com>
Date: Wed, 30 Aug 2017 17:57:14 +0300
Subject: [PATCH] Missing relocation R_PPC_VLE_ADDR20. Add VLE flag to details
in readelf.
---
bfd/ChangeLog | 7 +++++++
bfd/elf32-ppc.c | 37 +++++++++++++++++++++++++++++++++++++
binutils/ChangeLog | 6 ++++++
binutils/readelf.c | 11 +++++++++++
gas/ChangeLog | 7 +++++++
gas/config/tc-ppc.c | 20 ++++++++++++++++++++
gas/config/tc-ppc.h | 3 +++
include/ChangeLog | 5 +++++
include/elf/ppc.h | 1 +
9 files changed, 97 insertions(+)
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 4882260..eeb6382 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,10 @@
+2017-08-30 Alexander Fedotov <alexander.fedotov@nxp.com>
+ Edmar Wienskoski <edmar.wienskoski@nxp.com
+
+ * elf32-ppc.c (R_PPC_VLE_ADDR20): New relocation.
+ (ppc_elf_vle_split20): New function.
+ (ppc_elf_relocate_section): Handle R_PPC_VLE_ADDR20.
+
2017-08-30 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/22032
diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index 2bdba9f..da4adea 100644
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -1656,6 +1656,21 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
0x3e007ff, /* dst_mask */
FALSE), /* pcrel_offset */
+ /* e_li split20 format. */
+ HOWTO (R_PPC_VLE_ADDR20, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 20, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ bfd_elf_generic_reloc, /* special_function */
+ "R_PPC_VLE_ADDR20", /* name */
+ FALSE, /* partial_inplace */
+ 0, /* src_mask */
+ 0x1f07ff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
HOWTO (R_PPC_IRELATIVE, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@@ -4268,6 +4283,7 @@ ppc_elf_check_relocs (bfd *abfd,
case R_PPC_VLE_HI16D:
case R_PPC_VLE_HA16A:
case R_PPC_VLE_HA16D:
+ case R_PPC_VLE_ADDR20:
break;
case R_PPC_EMB_SDA2REL:
@@ -4986,6 +5002,23 @@ ppc_elf_vle_split16 (bfd *input_bfd,
insn |= value & 0x7ff;
bfd_put_32 (input_bfd, insn, loc);
}
+
+static void
+ppc_elf_vle_split20 (bfd *output_bfd, bfd_byte *loc, bfd_vma value)
+{
+ unsigned int insn;
+
+ insn = bfd_get_32 (output_bfd, loc);
+ /* We have an li20 field, bits 17..20, 11..15, 21..31. */
+ /* Top 4 bits of value to 17..20. */
+ insn |= (value & 0xf0000) >> 5;
+ /* Next 5 bits of the value to 11..15. */
+ insn |= (value & 0xf800) << 5;
+ /* And the final 11 bits of the value to bits 21 to 31. */
+ insn |= value & 0x7ff;
+ bfd_put_32 (output_bfd, insn, loc);
+}
+
/* Choose which PLT scheme to use, and set .plt flags appropriately.
Returns -1 on error, 0 for old PLT, 1 for new PLT. */
@@ -9512,6 +9545,10 @@ ppc_elf_relocate_section (bfd *output_bfd,
}
goto copy_reloc;
+ case R_PPC_VLE_ADDR20:
+ ppc_elf_vle_split20 (output_bfd, contents + rel->r_offset, relocation);
+ continue;
+
/* Relocate against the beginning of the section. */
case R_PPC_SECTOFF:
case R_PPC_SECTOFF_LO:
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 6d6aeee..d8a3de7 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,9 @@
+2017-08-30 Alexander Fedotov <alexander.fedotov@nxp.com>
+ Edmar Wienskoski <edmar.wienskoski@nxp.com
+
+ * readelf.c (get_elf_section_flags): Add VLE.
+ (process_section_headers): Add VLE key to details.
+
2017-08-25 Alan Modra <amodra@gmail.com>
PR 21994
diff --git a/binutils/readelf.c b/binutils/readelf.c
index db3fc03..571da2c 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -5587,6 +5587,8 @@ get_elf_section_flags (bfd_vma sh_flags)
/* 23 */ { STRING_COMMA_LEN ("COMDEF") },
/* GNU specific. */
/* 24 */ { STRING_COMMA_LEN ("GNU_MBIND") },
+ /* VLE specific. */
+ /* 25 */ { STRING_COMMA_LEN ("VLE") },
};
if (do_section_details)
@@ -5667,6 +5669,10 @@ get_elf_section_flags (bfd_vma sh_flags)
default: break;
}
break;
+ case EM_PPC:
+ if (flag == SHF_PPC_VLE)
+ sindex = 25;
+ break;
default:
break;
@@ -5724,6 +5730,9 @@ get_elf_section_flags (bfd_vma sh_flags)
else if (elf_header.e_machine == EM_ARM
&& flag == SHF_ARM_PURECODE)
*p = 'y';
+ else if (elf_header.e_machine == EM_PPC
+ && flag == SHF_PPC_VLE)
+ *p = 'v';
else if (flag & SHF_MASKOS)
{
*p = 'o';
@@ -6460,6 +6469,8 @@ process_section_headers (FILE * file)
printf (_("l (large), "));
else if (elf_header.e_machine == EM_ARM)
printf (_("y (purecode), "));
+ else if (elf_header.e_machine == EM_PPC)
+ printf (_("v (VLE), "));
printf ("p (processor specific)\n");
}
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2e60e29..51cdf0d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2017-08-30 Alexander Fedotov <alexander.fedotov@nxp.com>
+ Edmar Wienskoski <edmar.wienskoski@nxp.com
+
+ * config/tc-ppc.c (md_parse_option): Handle "mno-vle" flag.
+ (ppc_elf_section_letter): New function.
+ * config/tc-ppc.h (md_elf_section_letter): New.
+ * testsuite/gas/elf/section10.d: XFAIL for VLE
+
2017-08-30 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/gas/mips/branch-local-n32-2.d: Use `branch-local-2.l'
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index d20fac6..7118b71 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1206,6 +1206,16 @@ md_parse_option (int c, const char *arg)
}
}
+ else if (strcmp (arg, "no-vle") == 0)
+ {
+ sticky &= ~PPC_OPCODE_VLE;
+
+ new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, "booke");
+ new_cpu &= ~PPC_OPCODE_VLE;
+
+ ppc_cpu = new_cpu;
+ }
+
else if (strcmp (arg, "regnames") == 0)
reg_names_p = TRUE;
@@ -3683,6 +3693,16 @@ ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type)
return flags;
}
+
+bfd_vma
+ppc_elf_section_letter (int letter, const char **ptrmsg)
+{
+ if (letter == 'v')
+ return SHF_PPC_VLE;
+
+ *ptrmsg = _("bad .section directive: want a,e,v,w,x,M,S,G,T in string");
+ return -1;
+}
#endif /* OBJ_ELF */
diff --git a/gas/config/tc-ppc.h b/gas/config/tc-ppc.h
index 514c223..f71f2ea 100644
--- a/gas/config/tc-ppc.h
+++ b/gas/config/tc-ppc.h
@@ -226,6 +226,9 @@ extern int ppc_section_flags (flagword, bfd_vma, int);
#define tc_comment_chars ppc_comment_chars
extern const char *ppc_comment_chars;
+#define md_elf_section_letter ppc_elf_section_letter
+extern bfd_vma ppc_elf_section_letter (int, const char **);
+
/* Keep relocations relative to the GOT, or non-PC relative. */
#define tc_fix_adjustable(FIX) ppc_fix_adjustable (FIX)
extern int ppc_fix_adjustable (struct fix *);
diff --git a/gas/testsuite/gas/elf/section10.d b/gas/testsuite/gas/elf/section10.d
index e187263..dc7446f 100644
--- a/gas/testsuite/gas/elf/section10.d
+++ b/gas/testsuite/gas/elf/section10.d
@@ -1,7 +1,7 @@
#readelf: -N --wide
#name: numeric section flags and types
# The RX port annoyingly reorders the sections so that they do not match the sequence expected below.
-#skip: rx-*-*
+#skip: rx-*-* powerpc*-*-*vle
#...
[ ]*\[.*\][ ]+.text
diff --git a/include/ChangeLog b/include/ChangeLog
index d914f71..8f50361 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2017-08-30 Alexander Fedotov <alexander.fedotov@nxp.com>
+ Edmar Wienskoski <edmar.wienskoski@nxp.com
+
+ * elf/ppc.h (R_PPC_VLE_ADDR20): New relocation.
+
2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
Edmar Wienskoski <edmar.wienskoski@nxp.com>
diff --git a/include/elf/ppc.h b/include/elf/ppc.h
index 6790cd7..a7d2f3e 100644
--- a/include/elf/ppc.h
+++ b/include/elf/ppc.h
@@ -152,6 +152,7 @@ START_RELOC_NUMBERS (elf_ppc_reloc_type)
RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16D, 230)
RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16A, 231)
RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16D, 232)
+ RELOC_NUMBER (R_PPC_VLE_ADDR20, 233)
/* Power9 split rel16 for addpcis. */
RELOC_NUMBER (R_PPC_REL16DX_HA, 246)
--
2.7.4