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Re: [PATCH v2] RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2


On Tue, 24 Oct 2017 01:53:58 PDT (-0700), nickc@redhat.com wrote:
> Hi Palmer, Hi Andrew,
>
>> This matches the ISA specification.  This also adds two tests: one to
>> make sure the assembler rejects invalid 'c.lui's, and one to make sure
>> we only relax valid 'c.lui's.
>>
>> bfd/ChangeLog
>>
>> 2017-10-23  Andrew Waterman  <andrew@sifive.com>
>>
>>         * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui
>>         when rd is x0.
>>
>> include/ChangeLog
>>
>> 2017-10-23  Andrew Waterman  <andrew@sifive.com>
>>
>>         * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the
>>         immediate 0.
>>
>> gas/ChangeLog
>>
>> 2017-10-23  Andrew Waterman  <andrew@sifive.com>
>>
>>         * testsuite/gas/riscv/c-lui-fail.d: New testcase.
>>         gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
>>         gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
>>         gas/testsuite/gas/riscv/riscv.exp: Likewise.
>>
>> ld/ChangeLog
>>
>> 2017-10-23  Andrew Waterman  <andrew@sifive.com>
>>
>>         * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase.
>>         ld/testsuite/ld-riscv-elf/c-lui.s: Likewise.
>>         ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
>
> Thanks very much for making the changes.  Patch approved - please apply.

No problem -- it's always good to have tests, we've just been a bit lazy about
them.  We're hoping to pick up a bit more manpower so hopefully things will get
a bit smoother soon :).

I also noticed that I screwed up a ChangeLog entry, so I went ahead and fixed
it.

commit 3779bbe01b4ec1e5ae0a5c555f838999ba88ac50
Author: Palmer Dabbelt <palmer@dabbelt.com>
Date:   Tue Oct 24 06:58:48 2017 -0700

    Fix my previous gas/ChangeLog entry

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 138e43ceb4e8..7a9331df4325 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -12,8 +12,8 @@

 2017-10-23  Palmer Dabbelt  <palmer@dabbelt.com>

-        * config/tc-riscv.c (riscv_frag_align_code): Align code by 4
-        bytes on non-RVC systems.
+	* config/tc-riscv.c (riscv_frag_align_code): Align code by 4
+	bytes on non-RVC systems.

 2017-10-23  Maciej W. Rozycki  <macro@imgtec.com>

They're both committed.


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