This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH][GAS][AArch64] Add new command-line options and macros for Armv8.4-a [Patch (2/6)]
- From: Tamar Christina <tamar dot christina at arm dot com>
- To: binutils at sourceware dot org
- Cc: nd at arm dot com, Richard dot Earnshaw at arm dot com, marcus dot shawcroft at arm dot com
- Date: Wed, 8 Nov 2017 10:11:45 +0000
- Subject: [PATCH][GAS][AArch64] Add new command-line options and macros for Armv8.4-a [Patch (2/6)]
- Authentication-results: sourceware.org; auth=none
- Authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tamar dot Christina at arm dot com;
- Nodisclaimer: True
- Spamdiagnosticmetadata: NSPM
- Spamdiagnosticoutput: 1:99
Hi All,
This patch adds assembler and disassembler support for the new Armv8.4-a
command-line options and supporting feature macros for AArch64.
The support can be enabled through various new extensions which have all
been back-ported back to Armv8.2-a.
The new extensions are:
+sm4 - Includes support for the encryption algorithms in the
SM3 and SM4 class.
+sha3 - New SHA3 and SHA2 instructions added to Armv8.4-a and
back-ported to Armv8.2-a, implies SHA2
along with a new architecture "armv8.4-a".
These extensions can be used with Armv8.2-a and higher.
Checked with check-gas on aarch64-none-elf and aarch64_be-none-elf,
no regressions.
Ok for master?
Ps. I do not have commit access so if OK can someone apply for me?
Thanks,
Tamar
gas/
2017-11-08 Tamar Christina <tamar.christina@arm.com>
* config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a.
(aarch64_features): Added SM4 and SHA3.
include/
2017-11-08 Tamar Christina <tamar.christina@arm.com>
* opcode/aarch64.h:
(AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New.
(AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New.
opcodes/
2017-11-08 Tamar Christina <tamar.christina@arm.com>
* aarch64-tbl.h
(aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
(aarch64_feature_sm4, aarch64_feature_sha3): New.
(aarch64_feature_fp_16_v8_2): New.
(ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
(V8_4_INSN, CRYPTO_V8_2_INSN): New.
(SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
--
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index e85d38e5facdc5e348b4ba5a97db01f5c9815600..84b3dc7a84da9a9cc971e659debff42068455b65 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8463,6 +8463,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = {
{"armv8.1-a", AARCH64_ARCH_V8_1},
{"armv8.2-a", AARCH64_ARCH_V8_2},
{"armv8.3-a", AARCH64_ARCH_V8_3},
+ {"armv8.4-a", AARCH64_ARCH_V8_4},
{NULL, AARCH64_ARCH_NONE}
};
@@ -8514,6 +8515,11 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_ARCH_NONE},
{"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES, 0),
AARCH64_ARCH_NONE},
+ {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0),
+ AARCH64_ARCH_NONE},
+ {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
+ | AARCH64_FEATURE_SHA3, 0),
+ AARCH64_ARCH_NONE},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index eabff71a33bcac3724dbbda9475b2a64a42f2488..9e76952610ecb0c314f4971ea7f2b60282993bb0 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -39,6 +39,9 @@ typedef uint32_t aarch64_insn;
/* The following bitmasks control CPU features. */
#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
+#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
+#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
+#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
@@ -77,6 +80,8 @@ typedef uint32_t aarch64_insn;
AARCH64_FEATURE_V8_3 \
| AARCH64_FEATURE_RCPC \
| AARCH64_FEATURE_COMPNUM)
+#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
+ AARCH64_FEATURE_V8_4)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index dadb243239c50c96750945c9dec5168ed37b4cab..5ebd788e1f3e5340d06163e1b4022dda95629003 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2041,6 +2041,18 @@ static const aarch64_feature_set aarch64_feature_sha2 =
AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_SHA2, 0);
static const aarch64_feature_set aarch64_feature_aes =
AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_AES, 0);
+static const aarch64_feature_set aarch64_feature_v8_4 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_4, 0);
+static const aarch64_feature_set aarch64_feature_crypto_v8_2 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_CRYPTO, 0);
+static const aarch64_feature_set aarch64_feature_sm4 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SM4, 0);
+static const aarch64_feature_set aarch64_feature_sha3 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SHA2
+ | AARCH64_FEATURE_SHA3, 0);
+static const aarch64_feature_set aarch64_feature_fp_16_v8_2 =
+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F16
+ | AARCH64_FEATURE_FP, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2062,6 +2074,11 @@ static const aarch64_feature_set aarch64_feature_aes =
#define RCPC &aarch64_feature_rcpc
#define SHA2 &aarch64_feature_sha2
#define AES &aarch64_feature_aes
+#define ARMV8_4 &aarch64_feature_v8_4
+#define SHA3 &aarch64_feature_sha3
+#define SM4 &aarch64_feature_sm4
+#define CRYPTO_V8_2 &aarch64_feature_crypto_v8_2
+#define FP_F16_V8_2 &aarch64_feature_fp_16_v8_2
#define DOTPROD &aarch64_feature_dotprod
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
@@ -2099,6 +2116,16 @@ static const aarch64_feature_set aarch64_feature_aes =
{ NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, NULL }
#define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, NULL }
+#define V8_4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_4, OPS, QUALS, FLAGS, 0, NULL }
+#define CRYPTO_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, CRYPTO_V8_2, OPS, QUALS, FLAGS, 0, NULL }
+#define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, NULL }
+#define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, SM4, OPS, QUALS, FLAGS, 0, NULL }
+#define FP16_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, FP_F16_V8_2, OPS, QUALS, FLAGS, 0, NULL }
#define DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, NULL }