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[PATCH] x86/Intel: don't mistake riz/eiz as base register
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: <binutils at sourceware dot org>
- Date: Fri, 10 Nov 2017 04:51:25 -0700
- Subject: [PATCH] x86/Intel: don't mistake riz/eiz as base register
- Authentication-results: sourceware.org; auth=none
Just like we make rsp/esp a base register even if it comes second, make
riz/eiz an index register even if it comes first.
gas/
2017-11-10 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (i386_intel_simplify_register): Also
recognize RegRiz/RegEiz as index-only registers.
* testsuite/gas/i386/intel.s: Add tests exercising base/index
swapping.
* testsuite/gas/i386/intel.d: Adjust expectations.
--- 2017-11-10/gas/config/tc-i386-intel.c
+++ 2017-11-10/gas/config/tc-i386-intel.c
@@ -288,7 +288,9 @@ i386_intel_simplify_register (expression
else if (!intel_state.index
&& (i386_regtab[reg_num].reg_type.bitfield.regxmm
|| i386_regtab[reg_num].reg_type.bitfield.regymm
- || i386_regtab[reg_num].reg_type.bitfield.regzmm))
+ || i386_regtab[reg_num].reg_type.bitfield.regzmm
+ || i386_regtab[reg_num].reg_num == RegRiz
+ || i386_regtab[reg_num].reg_num == RegEiz))
intel_state.index = i386_regtab + reg_num;
else if (!intel_state.base && !intel_state.in_scale)
intel_state.base = i386_regtab + reg_num;
--- 2017-11-10/gas/testsuite/gas/i386/intel.d
+++ 2017-11-10/gas/testsuite/gas/i386/intel.d
@@ -698,6 +698,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%dx
[ ]*[a-f0-9]+: 66 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%dx
+[ ]*[a-f0-9]+: 8b 04 04 mov \(%esp,%eax(,1)?\),%eax
+[ ]*[a-f0-9]+: 8b 04 20 mov \(%eax(,%eiz)?(,1)?\),%eax
+[ ]*[a-f0-9]+: c4 e2 69 92 04 08 vgatherdps %xmm2,\(%eax,%xmm1(,1)?\),%xmm0
[ ]*[a-f0-9]+: 24 2f and \$0x2f,%al
[ ]*[a-f0-9]+: 0f \.byte 0xf
[a-f0-9]+ <barn>:
--- 2017-11-10/gas/testsuite/gas/i386/intel.s
+++ 2017-11-10/gas/testsuite/gas/i386/intel.s
@@ -699,6 +699,12 @@ fidivr dword ptr [ebx]
cmovpe dx, 0x90909090[eax]
cmovpo dx, 0x90909090[eax]
+ # Check base/index swapping
+ .allow_index_reg
+ mov eax, [eax+esp]
+ mov eax, [eiz+eax]
+ vgatherdps xmm0, [xmm1+eax], xmm2
+
# Test that disassembly of a partial instruction shows the partial byte:
# https://www.sourceware.org/ml/binutils/2015-08/msg00226.html
.byte 0x24