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[PATCH] x86: string insns don't allow displacements

From: "Jan Beulich" <JBeulich at suse dot com>
To: <binutils at sourceware dot org>
Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
Date: Fri, 10 Nov 2017 05:31:23 -0700
Subject: [PATCH] x86: string insns don't allow displacements
Authentication-results: sourceware.org; auth=none
x86: string insns don't allow displacements

Remove the misleading indicators from the table.

gas/
2017-11-10  Jan Beulich  <jbeulich@suse.com>

	* testsuite/gas/i386/string-ok.s: Add a few more valid patterns.
	Move bogus tests ...
	* testsuite/gas/i386/string-bad.s: ... here.
	* testsuite/gas/i386/string-bad.l: Adjust expectations.
	* testsuite/gas/i386/string-ok.d: Likewise.
	* testsuite/gas/i386/string-ok.e: Likewise.


opcodes/
2017-11-10  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
	smov, ssca, stos, ssto, xlat): Drop Disp*.
	* i386-tbl.h: Re-generate.

--- 2017-11-10/gas/testsuite/gas/i386/string-bad.l
+++ 2017-11-10/gas/testsuite/gas/i386/string-bad.l
@@ -6,12 +6,24 @@
 .*:8: Error: .*
 .*:9: Error: .*
 .*:10: Error: .*
-.*:14: Error: .*
+.*:11: Warning: .*
+.*:12: Warning: .*
+.*:13: Warning: .*
+.*:14: Warning: .*
+.*:15: Warning: .*
 .*:15: Error: .*
-.*:16: Error: .*
-.*:17: Error: .*
-.*:18: Error: .*
 .*:19: Error: .*
 .*:20: Error: .*
 .*:21: Error: .*
 .*:22: Error: .*
+.*:23: Error: .*
+.*:24: Error: .*
+.*:25: Error: .*
+.*:26: Error: .*
+.*:27: Error: .*
+.*:28: Warning: .*
+.*:29: Warning: .*
+.*:30: Warning: .*
+.*:31: Warning: .*
+.*:32: Warning: .*
+.*:32: Error: .*
--- 2017-11-10/gas/testsuite/gas/i386/string-bad.s
+++ 2017-11-10/gas/testsuite/gas/i386/string-bad.s
@@ -8,6 +8,11 @@ start:
 	cmpsb	%ds:(%edi), (%esi)
 	scasb	%ds:(%edi)
 	insb	(%dx), %ds:(%edi)
+	xlatb	(%esi)
+	xlatb	(,%ebx)
+	xlatb	1(%ebx)
+	xlatb	x(%ebx)
+	xlatb	0
 
 	.intel_syntax noprefix
 
@@ -20,3 +25,8 @@ start:
 	cmps	byte ptr [esi], dword ptr [edi]
 	scas	byte ptr ds:[edi]
 	ins	byte ptr ds:[edi], dx
+	xlat	byte ptr [esi]
+	xlat	byte ptr [%ebx*1]
+	xlat	byte ptr [ebx+1]
+	xlat	byte ptr x[ebx]
+	xlat	byte ptr FLAT:0
--- 2017-11-10/gas/testsuite/gas/i386/string-ok.d
+++ 2017-11-10/gas/testsuite/gas/i386/string-ok.d
@@ -26,12 +26,12 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:	ae[ 	]+scas   (%es:)?\(%edi\),%al
 [ 	]+[0-9a-f]+:	aa[ 	]+stos   %al,(%es:)?\(%edi\)
 [ 	]+[0-9a-f]+:	aa[ 	]+stos   %al,(%es:)?\(%edi\)
-[ 	]+[0-9a-f]+:	2e d7[ 	]+xlat   %cs:\(%ebx\)
-[ 	]+[0-9a-f]+:	d7[ 	]+xlat   (%ds:)?\(%ebx\)
-[ 	]+[0-9a-f]+:	d7[ 	]+xlat   (%ds:)?\(%ebx\)
-[ 	]+[0-9a-f]+:	d7[ 	]+xlat   (%ds:)?\(%ebx\)
-[ 	]+[0-9a-f]+:	d7[ 	]+xlat   (%ds:)?\(%ebx\)
-[ 	]+[0-9a-f]+:	d7[ 	]+xlat   (%ds:)?\(%ebx\)
+[ 	]+[0-9a-f]+:	d7[ 	]+xlatb? +(%ds:)?\(%ebx\)
+[ 	]+[0-9a-f]+:	67 d7[ 	]+xlatb? +(%ds:)?\(%bx\)
+[ 	]+[0-9a-f]+:	d7[ 	]+xlatb? +(%ds:)?\(%ebx\)
+[ 	]+[0-9a-f]+:	d7[ 	]+xlatb? +(%ds:)?\(%ebx\)
+[ 	]+[0-9a-f]+:	d7[ 	]+xlatb? +(%ds:)?\(%ebx\)
+[ 	]+[0-9a-f]+:	2e d7[ 	]+xlatb? +%cs:\(%ebx\)
 
 [0-9a-f]+ <.*start16>:
 [ 	]+[0-9a-f]+:	a6[ 	]+cmpsb  (%es:)?\(%edi\),(%ds:)?\(%esi\)
@@ -63,12 +63,11 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:	ae[ 	]+scas   (%es:)?\(%edi\),%al
 [ 	]+[0-9a-f]+:	aa[ 	]+stos   %al,(%es:)?\(%edi\)
 [ 	]+[0-9a-f]+:	aa[ 	]+stos   %al,(%es:)?\(%edi\)
-[ 	]+[0-9a-f]+:	2e d7[ 	]+xlat   %cs:\(%ebx\)
-[ 	]+[0-9a-f]+:	d7[ 	]+xlat   (%ds:)?\(%ebx\)
-[ 	]+[0-9a-f]+:	d7[ 	]+xlat   (%ds:)?\(%ebx\)
 [ 	]+[0-9a-f]+:	d7[ 	]+xlat   (%ds:)?\(%ebx\)
+[ 	]+[0-9a-f]+:	67 d7[ 	]+xlat   (%ds:)?\(%bx\)
 [ 	]+[0-9a-f]+:	d7[ 	]+xlat   (%ds:)?\(%ebx\)
 [ 	]+[0-9a-f]+:	d7[ 	]+xlat   (%ds:)?\(%ebx\)
+[ 	]+[0-9a-f]+:	2e d7[ 	]+xlat   %cs:\(%ebx\)
 
 [0-9a-f]+ <.*intel16>:
 [ 	]+[0-9a-f]+:	a6[ 	]+cmpsb  (%es:)?\(%edi\),(%ds:)?\(%esi\)
--- 2017-11-10/gas/testsuite/gas/i386/string-ok.e
+++ 2017-11-10/gas/testsuite/gas/i386/string-ok.e
@@ -8,11 +8,6 @@
 .*:22: Warning: .*
 .*:25: Warning: .*
 .*:28: Warning: .*
-.*:31: Warning: .*
-.*:32: Warning: .*
-.*:33: Warning: .*
-.*:34: Warning: .*
-.*:35: Warning: .*
 
 .*:54: Warning: .*
 .*:54: Warning: .*
@@ -23,8 +18,3 @@
 .*:70: Warning: .*
 .*:73: Warning: .*
 .*:76: Warning: .*
-.*:79: Warning: .*
-.*:80: Warning: .*
-.*:81: Warning: .*
-.*:82: Warning: .*
-.*:83: Warning: .*
--- 2017-11-10/gas/testsuite/gas/i386/string-ok.s
+++ 2017-11-10/gas/testsuite/gas/i386/string-ok.s
@@ -27,12 +27,12 @@ start32:
 	stosb	%es:(%edi)
 	stosb	(%esi)
 
+	xlat	(%ebx)
+	xlat	(%bx)
+	xlat	%ds:(%ebx)
+	xlatb
+	xlatb	(%ebx)
 	xlatb	%cs:(%ebx)
-	xlatb	(%esi)
-	xlatb	(,%ebx)
-	xlatb	1(%ebx)
-	xlatb	x(%ebx)
-	xlatb	0
 
 	.code16
 start16:
@@ -75,12 +75,11 @@ intel32:
 	stos	byte ptr es:[edi]
 	stos	byte ptr [esi]
 
+	xlatb
+	xlat	[bx]
+	xlat	ds:[ebx]
+	xlat	byte ptr [ebx]
 	xlat	byte ptr cs:[ebx]
-	xlat	byte ptr [esi]
-	xlat	byte ptr [%ebx*1]
-	xlat	byte ptr [ebx+1]
-	xlat	byte ptr x[ebx]
-	xlat	byte ptr FLAT:0
 
 	.code16
 intel16:
--- 2017-11-10/opcodes/i386-opc.tbl
+++ 2017-11-10/opcodes/i386-opc.tbl
@@ -437,37 +437,37 @@ setg, 1, 0xf9f, 0x0, 2, Cpu386, Modrm|No
 
 // String manipulation.
 cmps, 0, 0xa6, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-cmps, 2, 0xa6, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+cmps, 2, 0xa6, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 scmp, 0, 0xa6, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-scmp, 2, 0xa6, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+scmp, 2, 0xa6, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 ins, 0, 0x6c, None, 1, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-ins, 2, 0x6c, None, 1, Cpu186, W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
+ins, 2, 0x6c, None, 1, Cpu186, W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex|EsSeg }
 outs, 0, 0x6e, None, 1, Cpu186, W|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-outs, 2, 0x6e, None, 1, Cpu186, W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, InOutPortReg }
+outs, 2, 0x6e, None, 1, Cpu186, W|CheckRegSize|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg }
 lods, 0, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-lods, 1, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-lods, 2, 0xac, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc|Byte|Word|Dword|Qword }
+lods, 1, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+lods, 2, 0xac, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
 slod, 0, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-slod, 1, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-slod, 2, 0xac, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc|Byte|Word|Dword|Qword }
+slod, 1, 0xac, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+slod, 2, 0xac, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
 movs, 0, 0xa4, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-movs, 2, 0xa4, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
+movs, 2, 0xa4, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg }
 smov, 0, 0xa4, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-smov, 2, 0xa4, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
+smov, 2, 0xa4, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg }
 scas, 0, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-scas, 1, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
-scas, 2, 0xae, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc|Byte|Word|Dword|Qword }
+scas, 1, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg }
+scas, 2, 0xae, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg, Acc|Byte|Word|Dword|Qword }
 ssca, 0, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-ssca, 1, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
-ssca, 2, 0xae, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc|Byte|Word|Dword|Qword }
+ssca, 1, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg }
+ssca, 2, 0xae, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg, Acc|Byte|Word|Dword|Qword }
 stos, 0, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-stos, 1, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
-stos, 2, 0xaa, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
+stos, 1, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg }
+stos, 2, 0xaa, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg }
 ssto, 0, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-ssto, 1, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
-ssto, 2, 0xaa, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
+ssto, 1, 0xaa, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg }
+ssto, 2, 0xaa, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex|EsSeg }
 xlat, 0, 0xd7, None, 1, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { 0 }
-xlat, 1, 0xd7, None, 1, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+xlat, 1, 0xd7, None, 1, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString, { Byte|Unspecified|BaseIndex }
 
 // Bit manipulation.
 bsf, 2, 0xfbc, None, 2, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
Follow-Ups:
- Re: [PATCH] x86: string insns don't allow displacements
  - From: H.J. Lu
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